From patchwork Mon Jun 27 12:56:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1648918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LWnn36Sp6z9sGm for ; Mon, 27 Jun 2022 22:57:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 56393383DB96 for ; Mon, 27 Jun 2022 12:57:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id 3FD6D384145B for ; Mon, 27 Jun 2022 12:56:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3FD6D384145B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.92,226,1650960000"; d="scan'208";a="80572690" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa1.mentor.iphmx.com with ESMTP; 27 Jun 2022 04:56:37 -0800 IronPort-SDR: yrEkTtD4awMsCAvJNHEIg7D6NfIzFl0gsZOnL55lUHA6hQ52E3PbAmXH++udCAFTE2OGwusiUz BLXHdsqulvem360b8PhA4Tabl6MEueFG8C03m0cu4Y2osByBrktNx+yS4TJe2u7RWt5RyjYnPt MI2HlC7ms0OqwnL/rfa22H3/1hayqs25gtE31uhoRwaw7nVbjXzph/+VYaZGHldm3Utog+xMLw BDKKcuu8tedyi5ag3QF576UqLZMV9nVOKvBrWukNKWM2taLdunDRGXb4c8FO7qGgrk1RQYQ1SV RWQ= Message-ID: <6ef2f990-3d60-a3fa-57e1-d8dcc93823ee@codesourcery.com> Date: Mon, 27 Jun 2022 13:56:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-GB To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed] amdgcn: remove obsolete assembler workarounds X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-14.mgc.mentorg.com (139.181.222.14) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_STOCKGEN, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch removed some workarounds that were required for old versions of the LLVM assembler. The minimum supported version is now 13.0.1 so the workarounds are no longer needed. Andrew amdgcn: remove obsolete assembler workarounds This nonsense is no longer required, now that the minimum supported assembler version is LLVM 13.0.1. gcc/ChangeLog: * config/gcn/gcn.md (*movbi): Remove assembler bug workarounds. (jump): Likewise. (movdi_symbol_save_scc): Likewise. diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 53e846e15d1..033c1708e88 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -481,14 +481,7 @@ (define_insn "*movbi" we emit bytes directly as a workaround. */ switch (which_alternative) { case 0: - if (REG_P (operands[1]) && REGNO (operands[1]) == SCC_REG) - return "; s_mov_b32\t%0,%1 is not supported by the assembler.\;" - ".byte\t0xfd\;" - ".byte\t0x0\;" - ".byte\t0x80|%R0\;" - ".byte\t0xbe"; - else - return "s_mov_b32\t%0, %1"; + return "s_mov_b32\t%0, %1"; case 1: if (REG_P (operands[1]) && REGNO (operands[1]) == SCC_REG) return "; v_mov_b32\t%0, %1\;" @@ -505,16 +498,8 @@ (define_insn "*movbi" case 4: return "v_cmp_ne_u32\tvcc, 0, %1"; case 5: - if (REGNO (operands[1]) == SCC_REG) - return "; s_mov_b32\t%0, %1 is not supported by the assembler.\;" - ".byte\t0xfd\;" - ".byte\t0x0\;" - ".byte\t0xea\;" - ".byte\t0xbe\;" - "s_mov_b32\tvcc_hi, 0"; - else - return "s_mov_b32\tvcc_lo, %1\;" - "s_mov_b32\tvcc_hi, 0"; + return "s_mov_b32\tvcc_lo, %1\;" + "s_mov_b32\tvcc_hi, 0"; case 6: return "s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)"; case 7: @@ -739,8 +724,7 @@ (define_insn "jump" return "s_branch\t%0"; else /* !!! This sequence clobbers EXEC_SAVE_REG and CC_SAVE_REG. */ - return "; s_mov_b32\ts22, scc is not supported by the assembler.\;" - ".long\t0xbe9600fd\;" + return "s_mov_b32\ts22, scc\;" "s_getpc_b64\ts[20:21]\;" "s_add_u32\ts20, s20, %0@rel32@lo+4\;" "s_addc_u32\ts21, s21, %0@rel32@hi+4\;" @@ -801,11 +785,7 @@ (define_insn "cjump" } else return "s_cbranch%c1\t.Lskip%=\;" - "; s_mov_b32\ts22, scc is not supported by the assembler.\;" - ".byte\t0xfd\;" - ".byte\t0x0\;" - ".byte\t0x80|22\;" - ".byte\t0xbe\;" + "s_mov_b32\ts22, scc\;" "s_getpc_b64\ts[20:21]\;" "s_add_u32\ts20, s20, %0@rel32@lo+4\;" "s_addc_u32\ts21, s21, %0@rel32@hi+4\;" @@ -890,8 +870,7 @@ (define_insn "movdi_symbol_save_scc" if (SYMBOL_REF_P (operands[1]) && SYMBOL_REF_WEAK (operands[1])) - return "; s_mov_b32\ts22, scc is not supported by the assembler.\;" - ".long\t0xbe9600fd\;" + return "s_mov_b32\ts22, scc\;" "s_getpc_b64\t%0\;" "s_add_u32\t%L0, %L0, %1@gotpcrel32@lo+4\;" "s_addc_u32\t%H0, %H0, %1@gotpcrel32@hi+4\;" @@ -899,8 +878,7 @@ (define_insn "movdi_symbol_save_scc" "s_cmpk_lg_u32\ts22, 0\;" "s_waitcnt\tlgkmcnt(0)"; - return "; s_mov_b32\ts22, scc is not supported by the assembler.\;" - ".long\t0xbe9600fd\;" + return "s_mov_b32\ts22, scc\;" "s_getpc_b64\t%0\;" "s_add_u32\t%L0, %L0, %1@rel32@lo+4\;" "s_addc_u32\t%H0, %H0, %1@rel32@hi+4\;"