From patchwork Thu Dec 15 16:06:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 706160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tfdcT4d4vz9t0H for ; Fri, 16 Dec 2016 03:07:05 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Xokvqior"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=IuZ9QynSAulz4kBp5E8qWVZ2y9DzO T1f4NxxDEaRNlGmWCuYdV6M/MDzubrHVvM2GHKWDUvAlzZAAXUVdY/kedg9uexwj aQ4okQJRAl1R6x297M0N5tYZMj6J2b4jslT2F3PUghbwNDXCQhuxzwXqoV7ghmgS RyOqhuFGQZUMhU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=3AJj0flo4HTNJxVuBihUdfX8g6w=; b=Xok vqiorQnmV4cNw+37KxEjyD40uTxTHrfRDzK2AUzQrHw6PdT7lwQMmBdgdaX9jx/6 VWiwRTSqCMPg2XpqLeKYASNyUn6sqs6O95x4/KP4OIepSYoU1C9HOJzdBPo0zoC0 7UraDsjQ+bb08/HqMTTFSPo42qVtdyxVQLNPaL1A= Received: (qmail 32513 invoked by alias); 15 Dec 2016 16:06:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32468 invoked by uid 89); 15 Dec 2016 16:06:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:06:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0791E1516; Thu, 15 Dec 2016 08:06:02 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD9CF3F445 for ; Thu, 15 Dec 2016 08:06:01 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 06/21] [arm] Add new isa quirk bit for Cortex-M3 ldrd issue. To: gcc-patches@gcc.gnu.org References: Message-ID: <6b7efcd0-93f8-1fec-80b0-87b112f536f7@arm.com> Date: Thu, 15 Dec 2016 16:06:00 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: With the new data structures it is trivial to add a new field and we aren't (too) limited as to the number we have. This patch adds a new bit to describe the need for a particular compiler behaviour modification: in this case a quirk in the cortex-m3. * arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd. (ISA_ALL_QUIRKS): New macro. * arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list. * arm.c (isa_quirkbits): New feature-list bitmap. (arm_configure_build_target): Ignore quirk bits when comparing an architecture feature list with a CPU feature list. (arm_option_override): Initialize_isa_quirkbits. If the user has not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the feature if isa_quirk_cm3_ldrd appears in the isa feature list. --- gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm-isa.h | 9 ++++++++- gcc/config/arm/arm.c | 9 ++++++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 7c951f3..7f64a1f 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -160,7 +160,7 @@ ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex) ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7) ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m) -ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m) +ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m) ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4) /* V7 big.LITTLE implementations */ diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 15eb6e1..2d47c1b 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -58,9 +58,11 @@ enum isa_feature isa_bit_neon, /* Advanced SIMD instructions. */ isa_bit_fp16, /* FP16 extension (half-precision float). */ - /* ISA Quirks (errata?). */ + /* ISA Quirks (errata?). Don't forget to add this to the list of + all quirks below. */ isa_quirk_no_volatile_ce, /* No volatile memory in IT blocks. */ isa_quirk_ARMv6kz, /* Previously mis-identified by GCC. */ + isa_quirk_cm3_ldrd, /* Cortex-M3 LDRD quirk. */ /* Aren't currently, but probably should be tuning bits. */ isa_bit_smallmul, /* Slow multiply operations. */ @@ -120,6 +122,11 @@ enum isa_feature default. */ #define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_neon +/* List of all quirk bits to strip out when comparing CPU features with + architectures. */ +#define ISA_ALL_QUIRKS isa_quirk_no_volatile_ce, isa_quirk_ARMv6kz, \ + isa_quirk_cm3_ldrd + /* Helper macro so that we can concatenate multiple features together with arm-*.def files, since macro substitution can't have commas within an argument that lacks parenthesis. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3806226..c6be4d8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3056,6 +3056,7 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits) } static sbitmap isa_fpubits; +static sbitmap isa_quirkbits; /* Configure a build target TARGET from the user-specified options OPTS and OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and @@ -3097,6 +3098,8 @@ arm_configure_build_target (struct arm_build_target *target, arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits); bitmap_xor (cpu_isa, cpu_isa, target->isa); + /* Ignore any bits that are quirk bits. */ + bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits); /* Ignore (for now) any bits that might be set by -mfpu. */ bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits); @@ -3263,6 +3266,10 @@ static void arm_option_override (void) { static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit }; + static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit}; + + isa_quirkbits = sbitmap_alloc (isa_num_bits); + arm_initialize_isa (isa_quirkbits, quirk_bitlist); isa_fpubits = sbitmap_alloc (isa_num_bits); arm_initialize_isa (isa_fpubits, fpu_bitlist); @@ -3510,7 +3517,7 @@ arm_option_override (void) /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ if (fix_cm3_ldrd == 2) { - if (arm_selected_cpu->core == TARGET_CPU_cortexm3) + if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd)) fix_cm3_ldrd = 1; else fix_cm3_ldrd = 0;