From patchwork Mon Apr 10 12:12:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 748975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w1pwj2K8gz9sD5 for ; Mon, 10 Apr 2017 22:12:52 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="u7m0p1uJ"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=y6m8Ug5akwR11bPON Dtq6Erw0HoiVbPOsW42sIYQNQN9dbymU9pJX25VvDK4A/FogaY8NyBKgboMzC1da k5buLwJifCte6SF8iNJKvOWf+owGwnHd/M+BUJG7kapsFu2xt0QtiLOnQjOMqsAE +S13D2CF7cDsBNj07aR82pBF5E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=Hl1q0+4MpnICX2QsTDLvPrl 1tPw=; b=u7m0p1uJhKsnruH/OOcK1myNqe56JH/PPu4QWI7yK6AGNfr9etXud+y HMLwiD9WjEYjOa6zycD1rq2FuY34T3wh0EsnGrN6PlP1BL20HYHhDbLnjGuzSQ4E LLdKwiCL8rUIairwEMLoYYN3la6EAI4g9h04dBr9e6NVAOdmdkZ8= Received: (qmail 11700 invoked by alias); 10 Apr 2017 12:12:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 11661 invoked by uid 89); 10 Apr 2017 12:12:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=chip, Large, media, Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Apr 2017 12:12:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C129928; Mon, 10 Apr 2017 05:12:37 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB9393F4FF; Mon, 10 Apr 2017 05:12:36 -0700 (PDT) Subject: Re: [PATCH, GCC/ARM, gcc-5-branch] Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R To: Ramana Radhakrishnan References: Cc: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Message-ID: <66eefa85-d2c0-4b74-fd01-db137502e61a@foss.arm.com> Date: Mon, 10 Apr 2017 13:12:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Hi, Currently GCC is happy to use LDRD to perform a 64bit load on ARMv7-R, as shown by the testcase on this patch. However, LDRD is only atomic when LPAE extensions is available, which they are not for ARMv7-R. This commit solve the issue by introducing a new feature bit to distinguish LPAE extensions instead of deducing it from div instruction availability. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2017-03-22 Thomas Preud'homme PR target/80082 * config/arm/arm-protos.h (FL_LPAE): Define macro. (FL_FOR_ARCH7VE): Add FL_LPAE. (arm_arch_lpae): Declare extern. * config/arm/arm.c (arm_arch_lpae): Declare. (arm_option_override): Define arm_arch_lpae. * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of arm_arch_lpae. *** gcc/testsuite/ChangeLog *** 2017-03-22 Thomas Preud'homme PR target/80082 * gcc.target/arm/atomic_loaddi_10.c: New testcase. * gcc.target/arm/atomic_loaddi_11.c: Likewise. Is this ok for gcc-5-branch? Best regards, Thomas On 06/04/17 14:05, Ramana Radhakrishnan wrote: > On Mon, Mar 27, 2017 at 12:15 PM, Thomas Preudhomme > wrote: >> Hi, >> >> Currently GCC is happy to use LDRD to perform a 64bit load on ARMv7-R, >> as shown by the testcase on this patch. However, LDRD is only atomic >> when LPAE extensions is available, which they are not for ARMv7-R. This >> commit solve the issue by introducing a new feature bit to distinguish >> LPAE extensions instead of deducing it from div instruction >> availability. > > > Ok but with the testsuite fix that I just approved, please also fix > in gcc-5 branch. > > Thanks, > Ramana > >> >> ChangeLog entries are as follow: >> >> *** gcc/ChangeLog *** >> >> 2017-03-22 Thomas Preud'homme >> >> PR target/80082 >> * config/arm/arm-protos.h (FL_LPAE): Define macro. >> (FL_FOR_ARCH7VE): Add FL_LPAE. >> (arm_arch_lpae): Declare extern. >> * config/arm/arm.c (arm_arch_lpae): Declare. >> (arm_option_override): Define arm_arch_lpae. >> * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of >> arm_arch_lpae. >> >> *** gcc/testsuite/ChangeLog *** >> >> 2017-03-22 Thomas Preud'homme >> >> PR target/80082 >> * gcc.target/arm/atomic_loaddi_10.c: New testcase. >> * gcc.target/arm/atomic_loaddi_11.c: Likewise. >> >> >> Testing: bootstrapped for -march=armv7ve and testsuite shows no regression. >> >> Is this ok for gcc-6-branch? >> >> Best regards, >> >> Thomas diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index ebaf746227723f68c4c1cda89ba35c598a3ae4ba..21df391789d3d9f7b1d28e2bb2f99458843d0c3e 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -343,7 +343,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_STRONG (1 << 8) /* StrongARM */ #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ #define FL_XSCALE (1 << 10) /* XScale */ -/* spare (1 << 11) */ +#define FL_LPAE (1 << 11) /* ARMv7-A LPAE. */ #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds media instructions. */ #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ @@ -392,7 +392,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) -#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) +#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE) #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) @@ -487,6 +487,9 @@ extern int arm_arch_thumb2; extern int arm_arch_arm_hwdiv; extern int arm_arch_thumb_hwdiv; +/* Nonzero if this chip supports the Large Physical Address Extension. */ +extern int arm_arch_lpae; + /* Nonzero if chip disallows volatile memory access in IT block. */ extern int arm_arch_no_volatile_ce; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 5561e433b2929df311aec3263033c14b366836d3..4baf3e454b293c765c98948d86b23024ef84982d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -370,8 +370,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) /* Nonzero if this chip supports LPAE. */ -#define TARGET_HAVE_LPAE \ - (arm_arch7 && ((insn_flags & FL_FOR_ARCH7VE) == FL_FOR_ARCH7VE)) +#define TARGET_HAVE_LPAE (arm_arch_lpae) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6f9518995a387c84cd53deaa5ae6bac465d81ee8..c8aab8e09f83efd084a9d21e0d2fd04c04120877 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -866,6 +866,9 @@ int arm_arch_thumb2; int arm_arch_arm_hwdiv; int arm_arch_thumb_hwdiv; +/* Nonzero if this chip supports the Large Physical Address Extension. */ +int arm_arch_lpae; + /* Nonzero if chip disallows volatile memory access in IT block. */ int arm_arch_no_volatile_ce; @@ -2862,6 +2865,7 @@ arm_option_override (void) arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0; arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; + arm_arch_lpae = (insn_flags & FL_LPAE) != 0; arm_arch_no_volatile_ce = (insn_flags & FL_NO_VOLATILE_CE) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; arm_arch_crc = (insn_flags & FL_CRC32) != 0; diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c new file mode 100644 index 0000000000000000000000000000000000000000..ecc3d06d0c9f5966daa3ce7e2d52e09d14e0cbc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v7ve } */ + +#include + +atomic_llong x = 0; + +atomic_llong get_x() +{ + return atomic_load(&x); +} + +/* { dg-final { scan-assembler "ldrd" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c new file mode 100644 index 0000000000000000000000000000000000000000..85c64ae68b1b1ee68466809f7f83d07ceabec575 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v7r_ok } */ +/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */ +/* { dg-options "-O2 -mcpu=cortex-r5" } */ + +#include + +atomic_llong x = 0; + +atomic_llong get_x() +{ + return atomic_load(&x); +} + +/* { dg-final { scan-assembler-not "ldrd" } } */