@@ -5082,6 +5082,38 @@
operands[3] = gen_reg_rtx (DImode);
})
+;; Define optab for vector access with length vectorization exploitation.
+(define_expand "lenload<mode>qi"
+ [(match_operand:VEC_A 0 "vlogical_operand")
+ (match_operand:VEC_A 1 "memory_operand")
+ (match_operand:QI 2 "int_reg_operand")]
+ "TARGET_P9_VECTOR && TARGET_64BIT"
+{
+ rtx mem = XEXP (operands[1], 0);
+ mem = force_reg (DImode, mem);
+ rtx len = gen_lowpart (DImode, operands[2]);
+ rtx res = gen_reg_rtx (V16QImode);
+ emit_insn (gen_lxvl (res, mem, len));
+ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, res));
+ DONE;
+})
+
+(define_expand "lenstore<mode>qi"
+ [(match_operand:VEC_A 0 "memory_operand")
+ (match_operand:VEC_A 1 "vlogical_operand")
+ (match_operand:QI 2 "int_reg_operand")
+ ]
+ "TARGET_P9_VECTOR && TARGET_64BIT"
+{
+ rtx val = gen_reg_rtx (V16QImode);
+ emit_move_insn (val, gen_lowpart (V16QImode, operands[1]));
+ rtx mem = XEXP (operands[0], 0);
+ mem = force_reg (DImode, mem);
+ rtx len = gen_lowpart (DImode, operands[2]);
+ emit_insn (gen_stxvl (val, mem, len));
+ DONE;
+})
+
(define_insn "*stxvl"
[(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
(unspec:V16QI