From patchwork Tue May 10 13:26:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 620633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r40QF2XKMz9t45 for ; Tue, 10 May 2016 23:26:29 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=XChblWam; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version :content-transfer-encoding:content-type; q=dns; s=default; b=pXk QB1TIMkRzJs1moRHN7vbIVFM/DLaIMjfP4bI9nhkbYNVrsc//faXebyzfd0LiZ0l F8ypx7aJnr+bwSFDT7qpxkNaZbP2nMp65WqtjfxsIfFz5xTcHE3vLTxIngTcG81r TXtVTxcMDmRHGHoDWCSKMwVQJD3v5VNmecs7UTjA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=default; bh=ERKFFcpLb mA3ttH/IT6REHCLbc0=; b=XChblWamjffvwh+IviXMU4UuluB6jo8gpfXgeLq0R D4pwxpyWC5ZB9wy8FwJMtNMaoupnIx2K+9bLignzikuJwJwAYiDoaiDw4oAkQWqL IpUv2Fv3LCpdwfmQ6AWmyV4UXInSauu8VaN86oOJJKVTCeDzLEIYJncI0GB5JtWJ bM= Received: (qmail 61481 invoked by alias); 10 May 2016 13:26:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60855 invoked by uid 89); 10 May 2016 13:26:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=armh, UD:arm.h, arm.h, arm.c X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 10 May 2016 13:26:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 092E342B; Tue, 10 May 2016 06:26:21 -0700 (PDT) Received: from e108577-lin.localnet (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 762013F21A; Tue, 10 May 2016 06:26:09 -0700 (PDT) From: Thomas Preudhomme To: gcc-patches@gcc.gnu.org, kyrylo.tkachov@foss.arm.com, ramana.radhakrishnan@arm.com, richard.earnshaw@arm.com Subject: [PATCH, ARM] Do not set ARM_ARCH_ISA_THUMB for armv5 Date: Tue, 10 May 2016 14:26:04 +0100 Message-ID: <6455763.xNPUBGU9Kt@e108577-lin> User-Agent: KMail/4.13.3 (Linux/3.13.0-85-generic; KDE/4.13.3; x86_64; ; ) MIME-Version: 1.0 X-IsSubscribed: yes Hi, ARM_ARCH_ISA_THUMB is currently set to 1 when compiling for armv5 despite armv5 not supporting Thumb instructions (armv5t does): arm-none-eabi-gcc -dM -march=armv5 -E - < /dev/null | grep ISA_THUMB #define __ARM_ARCH_ISA_THUMB 1 The reason is TARGET_ARM_ARCH_ISA_THUMB being set to 1 if target does not support Thumb-2 and is ARMv4T, ARMv5 or later. This patch replaces that logic by checking whether the given architecture has the right feature bit (FL_THUMB). ChangeLog entry is as follows: *** gcc/ChangeLog *** 2016-05-06 Thomas Preud'homme * config/arm/arm-protos.h (arm_arch_thumb): Declare. * config/arm/arm.c (arm_arch_thumb): Define. (arm_option_override): Initialize arm_arch_thumb. * config/arm/arm.h (TARGET_ARM_ARCH_ISA_THUMB): Use arm_arch_thumb to determine if target support Thumb-1 ISA. Before patch: % arm-none-eabi-gcc -dM -march=armv4 -E - < /dev/null | grep ISA_THUMB cc1: warning: target CPU does not support THUMB instructions % arm-none-eabi-gcc -dM -march=armv4t -E - < /dev/null | grep ISA_THUMB #define __ARM_ARCH_ISA_THUMB 1 % arm-none-eabi-gcc -dM -march=armv5 -E - < /dev/null | grep ISA_THUMB cc1: warning: target CPU does not support THUMB instructions #define __ARM_ARCH_ISA_THUMB 1 % arm-none-eabi-gcc -dM -march=armv5t -E - < /dev/null | grep ISA_THUMB #define __ARM_ARCH_ISA_THUMB 1 After patch: % arm-none-eabi-gcc -dM -march=armv5 -E - < /dev/null | grep ISA_THUMB cc1: warning: target CPU does not support THUMB instructions % arm-none-eabi-gcc -dM -march=armv5t -E - < /dev/null | grep ISA_THUMB #define __ARM_ARCH_ISA_THUMB 1 % arm-none-eabi-gcc -dM -march=armv4 -E - < /dev/null | grep ISA_THUMB cc1: warning: target CPU does not support THUMB instructions % arm-none-eabi-gcc -dM -march=armv4t -E - < /dev/null | grep ISA_THUMB #define __ARM_ARCH_ISA_THUMB 1 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index d8179c441bb53dced94d2ebf497aad093e4ac600..4d11c91133ff1b875afcbf58abc4491c2c93768e 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -603,6 +603,9 @@ extern int arm_tune_cortex_a9; interworking clean. */ extern int arm_cpp_interwork; +/* Nonzero if chip supports Thumb. */ +extern int arm_arch_thumb; + /* Nonzero if chip supports Thumb 2. */ extern int arm_arch_thumb2; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ad123dde991a3e4c4b9563ee6ebb84981767988f..f64e8caa8bc08b7aff9fe385567de9936a964004 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2191,9 +2191,8 @@ extern int making_const_table; #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) /* The highest Thumb instruction set version supported by the chip. */ -#define TARGET_ARM_ARCH_ISA_THUMB \ - (arm_arch_thumb2 ? 2 \ - : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) +#define TARGET_ARM_ARCH_ISA_THUMB \ + (arm_arch_thumb2 ? 2 : (arm_arch_thumb ? 1 : 0)) /* Expands to an upper-case char of the target's architectural profile. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 71b51439dc7ba5be67671e9fb4c3f18040cce58f..de1c2d4600529518a92ed44815cff05308baa31c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -852,6 +852,9 @@ int arm_tune_cortex_a9 = 0; interworking clean. */ int arm_cpp_interwork = 0; +/* Nonzero if chip supports Thumb. */ +int arm_arch_thumb; + /* Nonzero if chip supports Thumb 2. */ int arm_arch_thumb2; @@ -3170,6 +3173,7 @@ arm_option_override (void) arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM); arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8); arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1); + arm_arch_thumb = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB); arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2); arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);