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Fri, 07 May 2021 15:53:35 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 147FrXl829295160 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 7 May 2021 15:53:34 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D5B506A064; Fri, 7 May 2021 15:53:33 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1A93D6A06F; Fri, 7 May 2021 15:53:33 +0000 (GMT) Received: from [9.160.71.72] (unknown [9.160.71.72]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 7 May 2021 15:53:32 +0000 (GMT) Subject: [PATCH, rs6000] Add ALTIVEC_REGS as pressure class To: GCC Patches Message-ID: <63c9b8a8-ff2f-cb54-6f97-ba8d401612d1@linux.ibm.com> Date: Fri, 7 May 2021 10:53:31 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: oBxczgjDS9oa5SUTNMY09442yWh8KuwQ X-Proofpoint-GUID: iLAtXfruxyJiijtqTBe7IwUj3fv-irSl X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-07_06:2021-05-06, 2021-05-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 mlxscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2105070106 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pat Haugen via Gcc-patches From: Pat Haugen Reply-To: Pat Haugen Cc: Peter Bergner , Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Add ALTIVEC_REGS as pressure class. Code that has heavy register pressure on Altivec registers can suffer from over-aggressive scheduling during sched1, which then leads to increased register spill. This is due to the fact that registers that prefer ALTIVEC_REGS are currently assigned an allocno class of VSX_REGS. This then misleads the scheduler to think there are 64 regs available, when in reality there are only 32 Altivec regs. This patch fixes the problem by assigning an allocno class of ALTIVEC_REGS and adding ALTIVEC_REGS as a pressure class. Bootstrap/regtest on powerpc64/powerpc64le with no new regressions. Testing on CPU2017 showed no significant differences. Ok for trunk? -Pat 2021-05-07 Pat Haugen gcc/ChangeLog: * config/rs6000/rs6000.c (rs6000_ira_change_pseudo_allocno_class): Return ALTIVEC_REGS if that is best_class. (rs6000_compute_pressure_classes): Add ALTIVEC_REGS. gcc/testsuite/ChangeLog: * gcc.target/powerpc/fold-vec-insert-float-p9.c: Adjust instruction counts. * gcc.target/powerpc/vec-rlmi-rlnm.c: Likewise. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 844fee8..fee4eef 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -22487,11 +22487,14 @@ rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED, of allocno class. */ if (best_class == BASE_REGS) return GENERAL_REGS; - if (TARGET_VSX - && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS)) + if (TARGET_VSX && best_class == FLOAT_REGS) return VSX_REGS; return best_class; + case VSX_REGS: + if (best_class == ALTIVEC_REGS) + return ALTIVEC_REGS; + default: break; } @@ -23609,12 +23612,12 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes) n = 0; pressure_classes[n++] = GENERAL_REGS; + if (TARGET_ALTIVEC) + pressure_classes[n++] = ALTIVEC_REGS; if (TARGET_VSX) pressure_classes[n++] = VSX_REGS; else { - if (TARGET_ALTIVEC) - pressure_classes[n++] = ALTIVEC_REGS; if (TARGET_HARD_FLOAT) pressure_classes[n++] = FLOAT_REGS; } diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c index 1c57672..4541768 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c @@ -31,5 +31,5 @@ testf_cst (float f, vector float vf) /* { dg-final { scan-assembler-times {\mstfs\M} 2 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\mxxperm\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mvperm\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mxxperm\M} 1 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c index 1e7d739..5512c0f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned long long y, /* { dg-final { scan-assembler-times "vextsb2d" 1 } } */ /* { dg-final { scan-assembler-times "vslw" 1 } } */ /* { dg-final { scan-assembler-times "vsld" 1 } } */ -/* { dg-final { scan-assembler-times "xxlor" 3 } } */ +/* { dg-final { scan-assembler-times "xxlor" 2 } } */ /* { dg-final { scan-assembler-times "vrlwnm" 2 } } */ /* { dg-final { scan-assembler-times "vrldnm" 2 } } */