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Wed, 15 May 2024 10:34:54 -0700 (PDT) Received: from [172.31.1.124] ([172.56.169.222]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-63411346d46sm10195956a12.79.2024.05.15.10.34.53 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 May 2024 10:34:53 -0700 (PDT) Message-ID: <6314375f-7e54-45a2-b02e-a20393fa68a5@ventanamicro.com> Date: Wed, 15 May 2024 11:34:50 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta From: Jeff Law Content-Language: en-US Subject: [to-be-committed][RISC-V] Improve some shift-add sequences To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org So this is a minor fix/improvement for shift-add sequences. This was supposed to help xz in a minor way IIRC. Combine may present us with (x + C2') << C1 which was canonicalized from (x << C1) + C2. Depending on the precise values of C2 and C2' one form may be better than the other. We can (somewhat awkwardly) use riscv_const_insns to test for which sequence would be preferred. Tested on Ventana's CI system as well as my own. Waiting on CI results from Rivos's tester before moving forward. Jeff gcc/ * config/riscv/riscv.md: Add new patterns to allow selection between (x << C1) + C2 vs (x + C2') << C1 depending on the cost C2 vs C2'. gcc/testsuite * gcc.target/riscv/shift-add-1.c: New test. commit 03933cf8813b28587ceb7f6f66ac03d08c5de58b Author: Jeff Law Date: Thu Apr 4 13:35:54 2024 -0600 Optimize (x << C1) + C2 after canonicalization to ((x + C2') << C1). C2' may have a lower cost to synthesize than C1. Reassociate to take advantage of that. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ffb09a4109d..69c80bc4a86 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4416,6 +4416,62 @@ (define_insn_and_split "" "{ operands[6] = gen_lowpart (SImode, operands[5]); }" [(set_attr "type" "arith")]) +;; These are forms of (x << C1) + C2, potentially canonicalized from +;; ((x + C2') << C1. Depending on the cost to load C2 vs C2' we may +;; want to go ahead and recognize this form as C2 may be cheaper to +;; synthesize than C2'. +;; +;; It might be better to refactor riscv_const_insns a bit so that we +;; can have an API that passes integer values around rather than +;; constructing a lot of garbage RTL. +;; +;; The mvconst_internal pattern in effect requires this pattern to +;; also be a define_insn_and_split due to insn count costing when +;; splitting in combine. +(define_insn_and_split "" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n")) + (match_operand 3 "const_int_operand" "n"))) + (clobber (match_scratch:DI 4 "=&r"))] + "(TARGET_64BIT + && riscv_const_insns (operands[3]) + && ((riscv_const_insns (operands[3]) + < riscv_const_insns (GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2])))) + || riscv_const_insns (GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2]))) == 0))" + "#" + "&& reload_completed" + [(set (match_dup 0) (ashift:DI (match_dup 1) (match_dup 2))) + (set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] + "" + [(set_attr "type" "arith")]) + +(define_insn_and_split "" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (plus:SI (ashift:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n")) + (match_operand 3 "const_int_operand" "n")))) + (clobber (match_scratch:DI 4 "=&r"))] + "(TARGET_64BIT + && riscv_const_insns (operands[3]) + && ((riscv_const_insns (operands[3]) + < riscv_const_insns (GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2])))) + || riscv_const_insns (GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2]))) == 0))" + "#" + "&& reload_completed" + [(set (match_dup 0) (ashift:DI (match_dup 1) (match_dup 2))) + (set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 6))))] + "{ + operands[1] = gen_lowpart (DImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_lowpart (SImode, operands[4]); + }" + [(set_attr "type" "arith")]) + + (include "bitmanip.md") (include "crypto.md") (include "sync.md") diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-1.c b/gcc/testsuite/gcc.target/riscv/shift-add-1.c new file mode 100644 index 00000000000..d98875c3271 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-add-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int composeFromSurrogate(const unsigned short high) { + + return ((high - 0xD800) << 10) ; +} + + +long composeFromSurrogate_2(const unsigned long high) { + + return ((high - 0xD800) << 10) ; +} + + +/* { dg-final { scan-assembler-times "\tli\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tslli\t" 2 } } */ +/* { dg-final { scan-assembler-times "\taddw\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tadd\t" 1 } } */ +