From patchwork Wed Sep 5 11:49:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 966332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-485168-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RGDYwy/s"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42528z0SQWz9s5c for ; Wed, 5 Sep 2018 21:51:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type; q=dns; s=default; b=MVp5Md+v9iXxNBzvvLz7C1aqtc0AT mQJyUesNHBkTVbdMa3AsswkaqTwnPuXcptJ4bD6o2LB0Jbng1S7d51cnW8SIqjOP xQtUmBH/lvRtcOmstVEGYubCdB0izJtTjTckWraNcOsEzTJJspuwuVrJVIE3/7Cl f/d8wxDgY8H9wY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type; s=default; bh=tf/470lf44t7XXA63vBeWzVy2dM=; b=RGD Ywy/seaosivX/SFegc1WOzWkQjaSm8RVBMJ/1X7scfhwOeDuYTaEhDyYLRCxmRcJ zgi3UPuI2KmoOwBwdBEh/bZsaP5RuA0KkeuqtjSL97EvONRA4+hx/GxVlGDP7jni A9r2Y/fZ87q47iTj+zCnjiypxssLMnVvZTnMCWGM= Received: (qmail 84059 invoked by alias); 5 Sep 2018 11:50:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 83953 invoked by uid 89); 5 Sep 2018 11:50:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.2 spammy=HX-detected-operating-system:Windows X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Sep 2018 11:50:02 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fxWJp-0002dG-Ej for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 07:50:00 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:45360) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fxWJp-0002cW-6Q for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 07:49:57 -0400 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=svr-ies-mbx-01.mgc.mentorg.com) by relay1.mentorg.com with esmtps (TLSv1.2:ECDHE-RSA-AES256-SHA384:256) id 1fxWJo-0005Yh-BA from Andrew_Stubbs@mentor.com for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 04:49:56 -0700 Received: from build6-trusty-cs.sje.mentorg.com (137.202.0.90) by svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Wed, 5 Sep 2018 12:49:52 +0100 From: To: Subject: [PATCH 06/25] Remove constant vec_select restriction. Date: Wed, 5 Sep 2018 12:49:38 +0100 Message-ID: <5f024fdd5ac905aa67cacdc932dcfb0b647675b6.1536144068.git.ams@codesourcery.com> In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 The vec_select operator is documented to require a const_int for the lane selector operand, but GCN has an instruction that can select the lane at runtime, so it seems reasonable to remove this restriction. This patch simply replaces assertions that the operand is constant with early exits from the optimizers. I think it's reasonable that vec_select with a non-constant operand cannot be optimized, yet. Also included is the necessary documentation tweak. 2018-09-05 Andrew Stubbs gcc/ * doc/rtl.texi: Adjust vec_select description. * simplify-rtx.c (simplify_binary_operation_1): Allow VEC_SELECT to use non-constant selectors. --- gcc/doc/rtl.texi | 11 ++++++----- gcc/simplify-rtx.c | 9 +++++++-- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index 5b1e695..0695ad2 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -2939,11 +2939,12 @@ a set bit indicates it is taken from @var{vec1}. @item (vec_select:@var{m} @var{vec1} @var{selection}) This describes an operation that selects parts of a vector. @var{vec1} is the source vector, and @var{selection} is a @code{parallel} that contains a -@code{const_int} for each of the subparts of the result vector, giving the -number of the source subpart that should be stored into it. -The result mode @var{m} is either the submode for a single element of -@var{vec1} (if only one subpart is selected), or another vector mode -with that element submode (if multiple subparts are selected). +@code{const_int} (or another expression, if the selection can be made at +runtime) for each of the subparts of the result vector, giving the number of +the source subpart that should be stored into it. The result mode @var{m} is +either the submode for a single element of @var{vec1} (if only one subpart is +selected), or another vector mode with that element submode (if multiple +subparts are selected). @findex vec_concat @item (vec_concat:@var{m} @var{x1} @var{x2}) diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index a9f2586..b4c6883 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -3604,7 +3604,10 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, gcc_assert (mode == GET_MODE_INNER (GET_MODE (trueop0))); gcc_assert (GET_CODE (trueop1) == PARALLEL); gcc_assert (XVECLEN (trueop1, 0) == 1); - gcc_assert (CONST_INT_P (XVECEXP (trueop1, 0, 0))); + + /* We can't reason about selections made at runtime. */ + if (!CONST_INT_P (XVECEXP (trueop1, 0, 0))) + return 0; if (vec_duplicate_p (trueop0, &elt0)) return elt0; @@ -3703,7 +3706,9 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, { rtx x = XVECEXP (trueop1, 0, i); - gcc_assert (CONST_INT_P (x)); + if (!CONST_INT_P (x)) + return 0; + RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, INTVAL (x)); }