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Sat, 18 May 2024 21:15:30 -0700 (PDT) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2ae2fcasm16987715b3a.123.2024.05.18.21.15.30 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 18 May 2024 21:15:30 -0700 (PDT) Message-ID: <5cc8e70b-f118-4245-8701-6fbc96df29eb@ventanamicro.com> Date: Sat, 18 May 2024 22:15:29 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta Content-Language: en-US To: "gcc-patches@gcc.gnu.org" From: Jeff Law Subject: [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Repost, this time with the RISC-V tag so it's picked up by the CI system. This fixes a minor bug that showed up in the CI system, presumably with fuzz testing. Under the right circumstances, we could end trying to emit a shift-add style sequence where the to-be-shifted operand was not a register. This naturally leads to an unrecognized insn. The circumstances which triggered this weren't something that should appear in the wild (-ftree-ter, without optimization enabled). So I wasn't planning to backport. Obviously if it shows up in another context we can revisit that decision. PR target/115142 gcc/ * config/riscv/riscv.cc (mem_shadd_or_shadd_rtx_p): Make sure shifted argument is a register. gcc/testsuite * gcc.target/riscv/pr115142.c: New test. I've run this through my rv32gcv and rv64gc tester. Waiting on the CI system before committing. jeff diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 7a34b4be873..d0c22058b8c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2465,6 +2465,7 @@ mem_shadd_or_shadd_rtx_p (rtx x) { return ((GET_CODE (x) == ASHIFT || GET_CODE (x) == MULT) + && register_operand (XEXP (x, 0), GET_MODE (x)) && CONST_INT_P (XEXP (x, 1)) && ((GET_CODE (x) == ASHIFT && IN_RANGE (INTVAL (XEXP (x, 1)), 1, 3)) || (GET_CODE (x) == MULT diff --git a/gcc/testsuite/gcc.target/riscv/pr115142.c b/gcc/testsuite/gcc.target/riscv/pr115142.c new file mode 100644 index 00000000000..40ba49dfa20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr115142.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -ftree-ter" } */ + +long a; +char b; +void e() { + char f[8][1]; + b = f[a][a]; +} +