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a=ed25519-sha256; c=relaxed/relaxed; t=1719832992; s=strato-dkim-0003; d=gjlay.de; h=Subject:To:From:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=D/m3DALX6tnsI37NfA5eAB4KIH73xPTPh/d0daxwnQs=; b=jK7PZ2OzVdKdxy40WwMfDgRFIpxN03P4cMVfpL4w9V7bgrQ/Q4J6FKENIUePBuMl+t TKF79EwEuFLfP5YjmNDQ== X-RZG-AUTH: ":LXoWVUeid/7A29J/hMvvT3koxZnKT7Qq0xotTetVnKkbjtK7q2y9LkX3jYYP" Received: from [192.168.2.102] by smtp.strato.de (RZmta 50.5.0 DYNA|AUTH) with ESMTPSA id x05778061BNCIbZ (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate) for ; Mon, 1 Jul 2024 13:23:12 +0200 (CEST) Message-ID: <5c2dea17-984c-4452-801e-1ffdcf394371@gjlay.de> Date: Mon, 1 Jul 2024 13:23:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Georg-Johann Lay Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [patch,avr,applied] PR88236, PR115726: Fix __memx code in the presence of hard regs. X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Applies this patch to fix code when the destination register overlaps with a hard register used by insn xload_A resp. xload8qi_A (PR115726). Also fixed PR88236 in one go because that PR is very similar in its outcome, and it's not possible to discriminate in a test case which is which, resp. when only one PR is fixed, test case will still fail. There are still tests that fail due to ICE FAIL: gcc.target/avr/torture/pr88236-pr115726.c -O3 -g (internal compiler error: in add_dwarf_attr, at dwarf2out.cc:4515) but that's a long standing bug not related to the PRs addressed by this patch. Johann --- AVR: target/88236, target/115726 - Fix __memx code generation. PR target/88236 PR target/115726 gcc/ * config/avr/avr.md (mov) [avr_mem_memx_p]: Expand in such a way that the destination does not overlap with any hard register clobbered / used by xload8qi_A resp. xload_A. * config/avr/avr.cc (avr_out_xload): Avoid early-clobber situation for Z by executing just one load when the output register overlaps with Z. gcc/testsuite/ * gcc.target/avr/torture/pr88236-pr115726.c: New test. diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 61c325f2497..a110af62cd5 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -4686,7 +4686,13 @@ avr_out_xload (rtx_insn * /*insn*/, rtx *op, int *plen) xop[2] = lpm_addr_reg_rtx; xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx; - avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1); + if (plen) + *plen = 0; + + if (reg_overlap_mentioned_p (xop[3], lpm_addr_reg_rtx)) + avr_asm_len ("sbrs %1,7", xop, plen, 1); + + avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1); avr_asm_len ("sbrc %1,7" CR_TAB "ld %3,%a2", xop, plen, 2); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 75d35d5e14b..dabf4c0fc5a 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -735,12 +735,26 @@ (define_expand "mov" if (!REG_P (addr)) src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr)); + rtx dest2 = reg_overlap_mentioned_p (dest, lpm_addr_reg_rtx) + ? gen_reg_rtx (mode) + : dest; + if (!avr_xload_libgcc_p (mode)) // No here because gen_xload8_A only iterates over ALL1. // insn-emit does not depend on the mode, it's all about operands. - emit_insn (gen_xload8qi_A (dest, src)); + emit_insn (gen_xload8qi_A (dest2, src)); else - emit_insn (gen_xload_A (dest, src)); + { + rtx reg_22 = gen_rtx_REG (mode, REG_22); + if (reg_overlap_mentioned_p (dest2, reg_22) + || reg_overlap_mentioned_p (dest2, all_regs_rtx[REG_21])) + dest2 = gen_reg_rtx (mode); + + emit_insn (gen_xload_A (dest2, src)); + } + + if (dest2 != dest) + emit_move_insn (dest, dest2); DONE; } diff --git a/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c new file mode 100644 index 00000000000..9fd5fd3b5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c @@ -0,0 +1,115 @@ +/* { dg-do run { target { ! avr_tiny } } } */ +/* { dg-additional-options "-std=gnu99" } */ + +const __flash char fvals8[] = { 1, 2, 3 }; +char rvals8[] = { 0, 2, 4 }; + +const __flash int fvals16[] = { 1, 2, 3 }; +int rvals16[] = { 0, 2, 4 }; + +__attribute__((noinline, noclone)) +char xload8_r30 (const __memx char *pc) +{ + register char c __asm ("r30"); + c = *pc; + __asm (";;" : "+r" (c)); + return c; +} + +__attribute__((noinline, noclone)) +int xload16_r30 (const __memx int *pc) +{ + register int c __asm ("r30"); + c = *pc; + __asm (";;" : "+r" (c)); + return c; +} + +__attribute__((noinline, noclone)) +char xload8_r22 (const __memx char *pc) +{ + register char c __asm ("r22"); + c = *pc; + __asm (";;" : "+r" (c)); + return c; +} + +__attribute__((noinline, noclone)) +int xload16_r22 (const __memx int *pc) +{ + register int c __asm ("r22"); + c = *pc; + __asm (";;" : "+r" (c)); + return c; +} + +__attribute__((noinline, noclone)) +int xload16_r20 (const __memx int *pc) +{ + register int c __asm ("r20"); + c = *pc; + __asm (";;" : "+r" (c)); + return c; +} + +void test8 (void) +{ + char c; + for (int i = 0; i < 3; ++i) + { + c = xload8_r30 (fvals8 + i); + if (c != 1 + i) + __builtin_exit (__LINE__); + + c = xload8_r22 (fvals8 + i); + if (c != 1 + i) + __builtin_exit (__LINE__); + + c = xload8_r30 (rvals8 + i); + if (c != 2 * i) + __builtin_exit (__LINE__); + + c = xload8_r22 (rvals8 + i); + if (c != 2 * i) + __builtin_exit (__LINE__); + } +} + +void test16 (void) +{ + int c; + for (int i = 0; i < 3; ++i) + { + c = xload16_r30 (fvals16 + i); + if (c != 1 + i) + __builtin_exit (__LINE__); + + c = xload16_r22 (fvals16 + i); + if (c != 1 + i) + __builtin_exit (__LINE__); + + c = xload16_r20 (fvals16 + i); + if (c != 1 + i) + __builtin_exit (__LINE__); + + c = xload16_r30 (rvals16 + i); + if (c != 2 * i) + __builtin_exit (__LINE__); + + c = xload16_r22 (rvals16 + i); + if (c != 2 * i) + __builtin_exit (__LINE__); + + c = xload16_r20 (rvals16 + i); + if (c != 2 * i) + __builtin_exit (__LINE__); + } +} + +int main (void) +{ + test8(); + test16(); + + return 0; +}