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[AArch64] Used prefer aliases SXTL(2) and UXTL(2)

Message ID 5B116A41.8060707@foss.arm.com
State New
Headers show
Series [AArch64] Used prefer aliases SXTL(2) and UXTL(2) | expand

Commit Message

Kyrill Tkachov June 1, 2018, 3:46 p.m. UTC 
Hi all,

The SSHL and USHL instructions are used with a shift operand of zero to
sign and zero-extend integer vectors into wider modes.
GCC makes extensive use of them to "unpack" vectors.

AArch64 defines a shorthand alias for that case. Instead of writing:
SSHLL <Vd>.<Ta>, <Vn>.<Tb>, 0

we can write

SXTL <Vd>.<Ta>, <Vn>.<Tb>

Similar for the unsigned versions and the high-part versions (SSHL2 -> SXTL2).
This makes the assembly of vectorised functions a bit more readable.

Bootstrapped and tested on aarch64-none-linux-gnu.

Committing to trunk as obvious.

Thanks,
Kyrill

2018-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64-simd.md
     (aarch64_simd_vec_unpack<su>_lo_<mode>): Use UXTL and SXTL assembler
     mnemonics.
     (aarch64_simd_vec_unpack<su>_hi_<mode>): Use UXTL2 and SXTL2 assembler
     mnemonics.
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Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index de059f6923546d3359a9b86dc7011b8ae8c80b82..d886b61f03751f7b76758cafed41c31e553b8e2a 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1567,7 +1567,7 @@  (define_insn "aarch64_simd_vec_unpack<su>_lo_<mode>"
 			       (match_operand:VQW 2 "vect_par_cnst_lo_half" "")
 			    )))]
   "TARGET_SIMD"
-  "<su>shll\t%0.<Vwtype>, %1.<Vhalftype>, 0"
+  "<su>xtl\t%0.<Vwtype>, %1.<Vhalftype>"
   [(set_attr "type" "neon_shift_imm_long")]
 )
 
@@ -1578,7 +1578,7 @@  (define_insn "aarch64_simd_vec_unpack<su>_hi_<mode>"
 			       (match_operand:VQW 2 "vect_par_cnst_hi_half" "")
 			    )))]
   "TARGET_SIMD"
-  "<su>shll2\t%0.<Vwtype>, %1.<Vtype>, 0"
+  "<su>xtl2\t%0.<Vwtype>, %1.<Vtype>"
   [(set_attr "type" "neon_shift_imm_long")]
 )