| Message ID | 5998649a-afec-4b1b-b638-18c14cf63c13@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [rs6000] Remove redundant guard for float128 mode patterns | expand |
Hi Haochen, on 2024/7/15 10:14, HAO CHEN GUI wrote: > Hi, > This patch removes FLOAT128_IEEE_P guard when the mode of pattern > is IEEE128 and FLOAT128_IBM_P when the mode of pattern is IBM128. > The mode iterators already do the checking. So they're redundant. > > Bootstrapped and tested on powerpc64-linux BE and LE with no > regressions. Is it OK for trunk? Thanks for this clean up, OK for trunk. BR, Kewen > > Thanks > Gui Haochen > > ChangeLog > rs6000: Remove redundant guard for float128 mode patterns > > gcc/ > * config/rs6000/rs6000.md (mov<mode>cc, *mov<mode>cc_p10, > *mov<mode>cc_invert_p10, *fpmask<mode>, *xxsel<mode>, > @ieee_128bit_vsx_abs<mode>2, *ieee_128bit_vsx_nabs<mode>2, > add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2, > copysign<mode>3, copysign<mode>3_hard, copysign<mode>3_soft, > @neg<mode>2_hw, @abs<mode>2_hw, *nabs<mode>2_hw, fma<mode>4_hw, > *fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw, > extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw, > trunc<mode>sf2_hw, fix<uns>_<IEEE128:mode><SDI:mode>2_hw, > fix<uns>_trunc<IEEE128:mode><QHI:mode>2, > *fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem, > float_<mode>di2_hw, float_<mode>si2_hw, > float<QHI:mode><IEEE128:mode>2, floatuns_<mode>di2_hw, > floatuns_<mode>si2_hw, floatuns<QHI:mode><IEEE128:mode>2, > floor<mode>2, ceil<mode>2, btrunc<mode>2, round<mode>2, > add<mode>3_odd, sub<mode>3_odd, mul<mode>3_odd, div<mode>3_odd, > sqrt<mode>2_odd, fma<mode>4_odd, *fms<mode>4_odd, *nfma<mode>4_odd, > *nfms<mode>4_odd, trunc<mode>df2_odd, *cmp<mode>_hw for IEEE128): > Remove guard FLOAT128_IEEE_P. > (@extenddf<mode>2_fprs, @extenddf<mode>2_vsx, > trunc<mode>df2_internal1, trunc<mode>df2_internal2, > fix_trunc_helper<mode>, neg<mode>2, *cmp<mode>_internal1, > *cmp<IBM128:mode>_internal2 for IBM128): Remove guard FLOAT128_IBM_P. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index c0f6599c08b..f22b7ed6256 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -5736,7 +5736,7 @@ (define_expand "mov<mode>cc" > (if_then_else:IEEE128 (match_operand 1 "comparison_operator") > (match_operand:IEEE128 2 "gpc_reg_operand") > (match_operand:IEEE128 3 "gpc_reg_operand")))] > - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > { > if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) > DONE; > @@ -5753,7 +5753,7 @@ (define_insn_and_split "*mov<mode>cc_p10" > (match_operand:IEEE128 4 "altivec_register_operand" "v,v") > (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) > (clobber (match_scratch:V2DI 6 "=0,&v"))] > - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > "#" > "&& 1" > [(set (match_dup 6) > @@ -5785,7 +5785,7 @@ (define_insn_and_split "*mov<mode>cc_invert_p10" > (match_operand:IEEE128 4 "altivec_register_operand" "v,v") > (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) > (clobber (match_scratch:V2DI 6 "=0,&v"))] > - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > "#" > "&& 1" > [(set (match_dup 6) > @@ -5820,7 +5820,7 @@ (define_insn "*fpmask<mode>" > (match_operand:IEEE128 3 "altivec_register_operand" "v")]) > (match_operand:V2DI 4 "all_ones_constant" "") > (match_operand:V2DI 5 "zero_constant" "")))] > - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > "xscmp%V1qp %0,%2,%3" > [(set_attr "type" "fpcompare")]) > > @@ -5831,7 +5831,7 @@ (define_insn "*xxsel<mode>" > (match_operand:V2DI 2 "zero_constant" "")) > (match_operand:IEEE128 3 "altivec_register_operand" "v") > (match_operand:IEEE128 4 "altivec_register_operand" "v")))] > - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_POWER10 && TARGET_FLOAT128_HW" > "xxsel %x0,%x4,%x3,%x1" > [(set_attr "type" "vecmove")]) > > @@ -8904,7 +8904,7 @@ (define_insn_and_split "@extenddf<mode>2_fprs" > (match_operand:DF 1 "nonimmediate_operand" "d,m,d"))) > (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))] > "!TARGET_VSX && TARGET_HARD_FLOAT > - && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)" > + && TARGET_LONG_DOUBLE_128" > "#" > "&& reload_completed" > [(set (match_dup 3) (match_dup 1)) > @@ -8921,7 +8921,7 @@ (define_insn_and_split "@extenddf<mode>2_vsx" > [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d") > (float_extend:IBM128 > (match_operand:DF 1 "nonimmediate_operand" "wa,m")))] > - "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)" > + "TARGET_LONG_DOUBLE_128 && TARGET_VSX" > "#" > "&& reload_completed" > [(set (match_dup 2) (match_dup 1)) > @@ -8967,7 +8967,7 @@ (define_insn_and_split "trunc<mode>df2_internal1" > [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") > (float_truncate:DF > (match_operand:IBM128 1 "gpc_reg_operand" "0,d")))] > - "FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT > + "!TARGET_XL_COMPAT > && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" > "@ > # > @@ -8983,7 +8983,7 @@ (define_insn_and_split "trunc<mode>df2_internal1" > (define_insn "trunc<mode>df2_internal2" > [(set (match_operand:DF 0 "gpc_reg_operand" "=d") > (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))] > - "FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT > + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT > && TARGET_LONG_DOUBLE_128" > "fadd %0,%1,%L1" > [(set_attr "type" "fp")]) > @@ -9036,7 +9036,7 @@ (define_insn "fix_trunc_helper<mode>" > (unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")] > UNSPEC_FIX_TRUNC_TF)) > (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))] > - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)" > + "TARGET_HARD_FLOAT" > "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" > [(set_attr "type" "fp") > (set_attr "length" "20")]) > @@ -9191,7 +9191,7 @@ (define_expand "neg<mode>2" > (define_insn "neg<mode>2_internal" > [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d") > (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))] > - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)" > + "TARGET_HARD_FLOAT" > { > if (REGNO (operands[0]) == REGNO (operands[1]) + 1) > return "fneg %L0,%L1\;fneg %0,%1"; > @@ -9313,7 +9313,7 @@ (define_insn_and_split "@ieee_128bit_vsx_abs<mode>2" > [(set (match_operand:IEEE128 0 "register_operand" "=wa") > (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) > (clobber (match_scratch:V16QI 2 "=v"))] > - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" > "#" > "&& 1" > [(parallel [(set (match_dup 0) > @@ -9343,8 +9343,7 @@ (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2" > (abs:IEEE128 > (match_operand:IEEE128 1 "register_operand" "wa")))) > (clobber (match_scratch:V16QI 2 "=v"))] > - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW > - && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" > "#" > "&& 1" > [(parallel [(set (match_dup 0) > @@ -12704,7 +12703,7 @@ (define_insn "*cmp<mode>_internal1" > [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") > (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d") > (match_operand:IBM128 2 "gpc_reg_operand" "d")))] > - "!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode) > + "!TARGET_XL_COMPAT > && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" > "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" > [(set_attr "type" "fpcompare") > @@ -12723,7 +12722,7 @@ (define_insn_and_split "*cmp<IBM128:mode>_internal2" > (clobber (match_scratch:DF 9 "=d")) > (clobber (match_scratch:DF 10 "=d")) > (clobber (match_scratch:GPR 11 "=b"))] > - "TARGET_XL_COMPAT && FLOAT128_IBM_P (<IBM128:MODE>mode) > + "TARGET_XL_COMPAT > && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" > "#" > "&& reload_completed" > @@ -15020,7 +15019,7 @@ (define_insn "add<mode>3" > (plus:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsaddqp %0,%1,%2" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15030,7 +15029,7 @@ (define_insn "sub<mode>3" > (minus:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xssubqp %0,%1,%2" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15040,7 +15039,7 @@ (define_insn "mul<mode>3" > (mult:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmulqp %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15050,7 +15049,7 @@ (define_insn "div<mode>3" > (div:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsdivqp %0,%1,%2" > [(set_attr "type" "vecdiv") > (set_attr "size" "128")]) > @@ -15059,7 +15058,7 @@ (define_insn "sqrt<mode>2" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (sqrt:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xssqrtqp %0,%1" > [(set_attr "type" "vecdiv") > (set_attr "size" "128")]) > @@ -15068,7 +15067,7 @@ (define_expand "copysign<mode>3" > [(use (match_operand:IEEE128 0 "altivec_register_operand")) > (use (match_operand:IEEE128 1 "altivec_register_operand")) > (use (match_operand:IEEE128 2 "any_operand"))] > - "FLOAT128_IEEE_P (<MODE>mode)" > + "" > { > /* Middle-end canonicalizes -fabs (x) to copysign (x, -1), > but PowerPC prefers -fabs (x). */ > @@ -15102,7 +15101,7 @@ (define_insn "copysign<mode>3_hard" > (copysign:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscpsgnqp %0,%2,%1" > [(set_attr "type" "vecmove") > (set_attr "size" "128")]) > @@ -15113,7 +15112,7 @@ (define_insn "copysign<mode>3_soft" > (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v"))) > (clobber (match_scratch:IEEE128 3 "=&v"))] > - "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "!TARGET_FLOAT128_HW" > "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" > [(set_attr "type" "veccomplex") > (set_attr "length" "8")]) > @@ -15122,7 +15121,7 @@ (define_insn "@neg<mode>2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (neg:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnegqp %0,%1" > [(set_attr "type" "vecmove") > (set_attr "size" "128")]) > @@ -15132,7 +15131,7 @@ (define_insn "@abs<mode>2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (abs:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsabsqp %0,%1" > [(set_attr "type" "vecmove") > (set_attr "size" "128")]) > @@ -15143,7 +15142,7 @@ (define_insn "*nabs<mode>2_hw" > (neg:IEEE128 > (abs:IEEE128 > (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnabsqp %0,%1" > [(set_attr "type" "vecmove") > (set_attr "size" "128")]) > @@ -15155,7 +15154,7 @@ (define_insn "fma<mode>4_hw" > (match_operand:IEEE128 1 "altivec_register_operand" "%v") > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (match_operand:IEEE128 3 "altivec_register_operand" "0")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmaddqp %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15167,7 +15166,7 @@ (define_insn "*fms<mode>4_hw" > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (neg:IEEE128 > (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmsubqp %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15179,7 +15178,7 @@ (define_insn "*nfma<mode>4_hw" > (match_operand:IEEE128 1 "altivec_register_operand" "%v") > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnmaddqp %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15192,7 +15191,7 @@ (define_insn "*nfms<mode>4_hw" > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (neg:IEEE128 > (match_operand:IEEE128 3 "altivec_register_operand" "0")))))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnmsubqp %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15201,7 +15200,7 @@ (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (float_extend:IEEE128 > (match_operand:SFDF 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvdpqp %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15244,7 +15243,7 @@ (define_insn "trunc<mode>df2_hw" > [(set (match_operand:DF 0 "altivec_register_operand" "=v") > (float_truncate:DF > (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvqpdp %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15257,7 +15256,7 @@ (define_insn_and_split "trunc<mode>sf2_hw" > (float_truncate:SF > (match_operand:IEEE128 1 "altivec_register_operand" "v"))) > (clobber (match_scratch:DF 2 "=v"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& 1" > [(set (match_dup 2) > @@ -15287,7 +15286,7 @@ (define_insn_and_split "trunc<mode>sf2_hw" > (define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw" > [(set (match_operand:SDI 0 "altivec_register_operand" "=v") > (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvqp<su><wd>z %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15296,7 +15295,7 @@ (define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>2" > [(set (match_operand:QHI 0 "altivec_register_operand" "=v") > (any_fix:QHI > (match_operand:IEEE128 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvqp<su>wz %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15308,7 +15307,7 @@ (define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem" > (any_fix:QHSI > (match_operand:IEEE128 1 "altivec_register_operand" "v"))) > (clobber (match_scratch:QHSI 2 "=v"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& reload_completed" > [(set (match_dup 2) > @@ -15319,7 +15318,7 @@ (define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem" > (define_insn "float_<mode>di2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvsdqp %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15328,7 +15327,7 @@ (define_insn_and_split "float_<mode>si2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) > (clobber (match_scratch:DI 2 "=v"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& 1" > [(set (match_dup 2) > @@ -15347,7 +15346,7 @@ (define_insn_and_split "float<QHI:mode><IEEE128:mode>2" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") > (float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) > (clobber (match_scratch:DI 2 "=X,r,X"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& reload_completed" > [(const_int 0)] > @@ -15384,7 +15383,7 @@ (define_insn "floatuns_<mode>di2_hw" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > (unsigned_float:IEEE128 > (match_operand:DI 1 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvudqp %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15394,7 +15393,7 @@ (define_insn_and_split "floatuns_<mode>si2_hw" > (unsigned_float:IEEE128 > (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) > (clobber (match_scratch:DI 2 "=v"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& 1" > [(set (match_dup 2) > @@ -15414,7 +15413,7 @@ (define_insn_and_split "floatuns<QHI:mode><IEEE128:mode>2" > (unsigned_float:IEEE128 > (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) > (clobber (match_scratch:DI 2 "=X,r,X"))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" > + "TARGET_FLOAT128_HW" > "#" > "&& reload_completed" > [(const_int 0)] > @@ -15447,7 +15446,7 @@ (define_insn "floor<mode>2" > (unspec:IEEE128 > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_FRIM))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsrqpi 1,%0,%1,3" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15457,7 +15456,7 @@ (define_insn "ceil<mode>2" > (unspec:IEEE128 > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_FRIP))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsrqpi 1,%0,%1,2" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15467,7 +15466,7 @@ (define_insn "btrunc<mode>2" > (unspec:IEEE128 > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_FRIZ))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsrqpi 1,%0,%1,1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15477,7 +15476,7 @@ (define_insn "round<mode>2" > (unspec:IEEE128 > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_FRIN))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsrqpi 0,%0,%1,0" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15489,7 +15488,7 @@ (define_insn "add<mode>3_odd" > [(match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")] > UNSPEC_ADD_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsaddqpo %0,%1,%2" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15500,7 +15499,7 @@ (define_insn "sub<mode>3_odd" > [(match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")] > UNSPEC_SUB_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xssubqpo %0,%1,%2" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15511,7 +15510,7 @@ (define_insn "mul<mode>3_odd" > [(match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")] > UNSPEC_MUL_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmulqpo %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15522,7 +15521,7 @@ (define_insn "div<mode>3_odd" > [(match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")] > UNSPEC_DIV_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsdivqpo %0,%1,%2" > [(set_attr "type" "vecdiv") > (set_attr "size" "128")]) > @@ -15532,7 +15531,7 @@ (define_insn "sqrt<mode>2_odd" > (unspec:IEEE128 > [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_SQRT_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xssqrtqpo %0,%1" > [(set_attr "type" "vecdiv") > (set_attr "size" "128")]) > @@ -15544,7 +15543,7 @@ (define_insn "fma<mode>4_odd" > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (match_operand:IEEE128 3 "altivec_register_operand" "0")] > UNSPEC_FMA_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmaddqpo %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15557,7 +15556,7 @@ (define_insn "*fms<mode>4_odd" > (neg:IEEE128 > (match_operand:IEEE128 3 "altivec_register_operand" "0"))] > UNSPEC_FMA_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsmsubqpo %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15570,7 +15569,7 @@ (define_insn "*nfma<mode>4_odd" > (match_operand:IEEE128 2 "altivec_register_operand" "v") > (match_operand:IEEE128 3 "altivec_register_operand" "0")] > UNSPEC_FMA_ROUND_TO_ODD)))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnmaddqpo %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15584,7 +15583,7 @@ (define_insn "*nfms<mode>4_odd" > (neg:IEEE128 > (match_operand:IEEE128 3 "altivec_register_operand" "0"))] > UNSPEC_FMA_ROUND_TO_ODD)))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xsnmsubqpo %0,%1,%2" > [(set_attr "type" "qmul") > (set_attr "size" "128")]) > @@ -15593,7 +15592,7 @@ (define_insn "trunc<mode>df2_odd" > [(set (match_operand:DF 0 "vsx_register_operand" "=v") > (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > UNSPEC_TRUNC_ROUND_TO_ODD))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscvqpdpo %0,%1" > [(set_attr "type" "vecfloat") > (set_attr "size" "128")]) > @@ -15603,7 +15602,7 @@ (define_insn "*cmp<mode>_hw" > [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") > (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") > (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > + "TARGET_FLOAT128_HW" > "xscmpuqp %0,%1,%2" > [(set_attr "type" "veccmp") > (set_attr "size" "128")])
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c0f6599c08b..f22b7ed6256 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5736,7 +5736,7 @@ (define_expand "mov<mode>cc" (if_then_else:IEEE128 (match_operand 1 "comparison_operator") (match_operand:IEEE128 2 "gpc_reg_operand") (match_operand:IEEE128 3 "gpc_reg_operand")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; @@ -5753,7 +5753,7 @@ (define_insn_and_split "*mov<mode>cc_p10" (match_operand:IEEE128 4 "altivec_register_operand" "v,v") (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) (clobber (match_scratch:V2DI 6 "=0,&v"))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 6) @@ -5785,7 +5785,7 @@ (define_insn_and_split "*mov<mode>cc_invert_p10" (match_operand:IEEE128 4 "altivec_register_operand" "v,v") (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) (clobber (match_scratch:V2DI 6 "=0,&v"))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 6) @@ -5820,7 +5820,7 @@ (define_insn "*fpmask<mode>" (match_operand:IEEE128 3 "altivec_register_operand" "v")]) (match_operand:V2DI 4 "all_ones_constant" "") (match_operand:V2DI 5 "zero_constant" "")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "xscmp%V1qp %0,%2,%3" [(set_attr "type" "fpcompare")]) @@ -5831,7 +5831,7 @@ (define_insn "*xxsel<mode>" (match_operand:V2DI 2 "zero_constant" "")) (match_operand:IEEE128 3 "altivec_register_operand" "v") (match_operand:IEEE128 4 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "xxsel %x0,%x4,%x3,%x1" [(set_attr "type" "vecmove")]) @@ -8904,7 +8904,7 @@ (define_insn_and_split "@extenddf<mode>2_fprs" (match_operand:DF 1 "nonimmediate_operand" "d,m,d"))) (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))] "!TARGET_VSX && TARGET_HARD_FLOAT - && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)" + && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 1)) @@ -8921,7 +8921,7 @@ (define_insn_and_split "@extenddf<mode>2_vsx" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d") (float_extend:IBM128 (match_operand:DF 1 "nonimmediate_operand" "wa,m")))] - "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)" + "TARGET_LONG_DOUBLE_128 && TARGET_VSX" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 1)) @@ -8967,7 +8967,7 @@ (define_insn_and_split "trunc<mode>df2_internal1" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "0,d")))] - "FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "@ # @@ -8983,7 +8983,7 @@ (define_insn_and_split "trunc<mode>df2_internal1" (define_insn "trunc<mode>df2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))] - "FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "fadd %0,%1,%L1" [(set_attr "type" "fp")]) @@ -9036,7 +9036,7 @@ (define_insn "fix_trunc_helper<mode>" (unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")] UNSPEC_FIX_TRUNC_TF)) (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))] - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)" + "TARGET_HARD_FLOAT" "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" [(set_attr "type" "fp") (set_attr "length" "20")]) @@ -9191,7 +9191,7 @@ (define_expand "neg<mode>2" (define_insn "neg<mode>2_internal" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d") (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)" + "TARGET_HARD_FLOAT" { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) return "fneg %L0,%L1\;fneg %0,%1"; @@ -9313,7 +9313,7 @@ (define_insn_and_split "@ieee_128bit_vsx_abs<mode>2" [(set (match_operand:IEEE128 0 "register_operand" "=wa") (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) (clobber (match_scratch:V16QI 2 "=v"))] - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" "#" "&& 1" [(parallel [(set (match_dup 0) @@ -9343,8 +9343,7 @@ (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2" (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))) (clobber (match_scratch:V16QI 2 "=v"))] - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" "#" "&& 1" [(parallel [(set (match_dup 0) @@ -12704,7 +12703,7 @@ (define_insn "*cmp<mode>_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d") (match_operand:IBM128 2 "gpc_reg_operand" "d")))] - "!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode) + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" [(set_attr "type" "fpcompare") @@ -12723,7 +12722,7 @@ (define_insn_and_split "*cmp<IBM128:mode>_internal2" (clobber (match_scratch:DF 9 "=d")) (clobber (match_scratch:DF 10 "=d")) (clobber (match_scratch:GPR 11 "=b"))] - "TARGET_XL_COMPAT && FLOAT128_IBM_P (<IBM128:MODE>mode) + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" @@ -15020,7 +15019,7 @@ (define_insn "add<mode>3" (plus:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsaddqp %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15030,7 +15029,7 @@ (define_insn "sub<mode>3" (minus:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xssubqp %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15040,7 +15039,7 @@ (define_insn "mul<mode>3" (mult:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmulqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15050,7 +15049,7 @@ (define_insn "div<mode>3" (div:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsdivqp %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15059,7 +15058,7 @@ (define_insn "sqrt<mode>2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (sqrt:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xssqrtqp %0,%1" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15068,7 +15067,7 @@ (define_expand "copysign<mode>3" [(use (match_operand:IEEE128 0 "altivec_register_operand")) (use (match_operand:IEEE128 1 "altivec_register_operand")) (use (match_operand:IEEE128 2 "any_operand"))] - "FLOAT128_IEEE_P (<MODE>mode)" + "" { /* Middle-end canonicalizes -fabs (x) to copysign (x, -1), but PowerPC prefers -fabs (x). */ @@ -15102,7 +15101,7 @@ (define_insn "copysign<mode>3_hard" (copysign:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscpsgnqp %0,%2,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15113,7 +15112,7 @@ (define_insn "copysign<mode>3_soft" (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v"))) (clobber (match_scratch:IEEE128 3 "=&v"))] - "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "!TARGET_FLOAT128_HW" "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" [(set_attr "type" "veccomplex") (set_attr "length" "8")]) @@ -15122,7 +15121,7 @@ (define_insn "@neg<mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnegqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15132,7 +15131,7 @@ (define_insn "@abs<mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (abs:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsabsqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15143,7 +15142,7 @@ (define_insn "*nabs<mode>2_hw" (neg:IEEE128 (abs:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnabsqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15155,7 +15154,7 @@ (define_insn "fma<mode>4_hw" (match_operand:IEEE128 1 "altivec_register_operand" "%v") (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmaddqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15167,7 +15166,7 @@ (define_insn "*fms<mode>4_hw" (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmsubqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15179,7 +15178,7 @@ (define_insn "*nfma<mode>4_hw" (match_operand:IEEE128 1 "altivec_register_operand" "%v") (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnmaddqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15192,7 +15191,7 @@ (define_insn "*nfms<mode>4_hw" (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0")))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnmsubqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15201,7 +15200,7 @@ (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float_extend:IEEE128 (match_operand:SFDF 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "xscvdpqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15244,7 +15243,7 @@ (define_insn "trunc<mode>df2_hw" [(set (match_operand:DF 0 "altivec_register_operand" "=v") (float_truncate:DF (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscvqpdp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15257,7 +15256,7 @@ (define_insn_and_split "trunc<mode>sf2_hw" (float_truncate:SF (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:DF 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15287,7 +15286,7 @@ (define_insn_and_split "trunc<mode>sf2_hw" (define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw" [(set (match_operand:SDI 0 "altivec_register_operand" "=v") (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "xscvqp<su><wd>z %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15296,7 +15295,7 @@ (define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>2" [(set (match_operand:QHI 0 "altivec_register_operand" "=v") (any_fix:QHI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "xscvqp<su>wz %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15308,7 +15307,7 @@ (define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem" (any_fix:QHSI (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:QHSI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(set (match_dup 2) @@ -15319,7 +15318,7 @@ (define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem" (define_insn "float_<mode>di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscvsdqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15328,7 +15327,7 @@ (define_insn_and_split "float_<mode>si2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) (clobber (match_scratch:DI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15347,7 +15346,7 @@ (define_insn_and_split "float<QHI:mode><IEEE128:mode>2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") (float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=X,r,X"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(const_int 0)] @@ -15384,7 +15383,7 @@ (define_insn "floatuns_<mode>di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unsigned_float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscvudqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15394,7 +15393,7 @@ (define_insn_and_split "floatuns_<mode>si2_hw" (unsigned_float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) (clobber (match_scratch:DI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15414,7 +15413,7 @@ (define_insn_and_split "floatuns<QHI:mode><IEEE128:mode>2" (unsigned_float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=X,r,X"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(const_int 0)] @@ -15447,7 +15446,7 @@ (define_insn "floor<mode>2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIM))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,3" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15457,7 +15456,7 @@ (define_insn "ceil<mode>2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIP))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15467,7 +15466,7 @@ (define_insn "btrunc<mode>2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIZ))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15477,7 +15476,7 @@ (define_insn "round<mode>2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIN))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsrqpi 0,%0,%1,0" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15489,7 +15488,7 @@ (define_insn "add<mode>3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsaddqpo %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15500,7 +15499,7 @@ (define_insn "sub<mode>3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xssubqpo %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15511,7 +15510,7 @@ (define_insn "mul<mode>3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmulqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15522,7 +15521,7 @@ (define_insn "div<mode>3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsdivqpo %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15532,7 +15531,7 @@ (define_insn "sqrt<mode>2_odd" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xssqrtqpo %0,%1" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15544,7 +15543,7 @@ (define_insn "fma<mode>4_odd" (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmaddqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15557,7 +15556,7 @@ (define_insn "*fms<mode>4_odd" (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsmsubqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15570,7 +15569,7 @@ (define_insn "*nfma<mode>4_odd" (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnmaddqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15584,7 +15583,7 @@ (define_insn "*nfms<mode>4_odd" (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xsnmsubqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15593,7 +15592,7 @@ (define_insn "trunc<mode>df2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_TRUNC_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscvqpdpo %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15603,7 +15602,7 @@ (define_insn "*cmp<mode>_hw" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "TARGET_FLOAT128_HW" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") (set_attr "size" "128")])