From patchwork Tue Dec 6 11:36:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 703099 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tY03P4dXkz9vGw for ; Tue, 6 Dec 2016 22:37:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mDOCBt/T"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=KeMBnSwExtvq4dlX+ su1CEtjGUTO2miNPar54zxceMAv6G4oVczQZ9nEAOmVMaxAaY7065HJ+2zm1QZeh 4vZ2df1NPvlBZS+p0AhwK1Z40u9TT+aSzP/pcXRUTXYSQotH4p3b/36RjNP7OiDR 4jmHFlNzHwDnKWA65RTnohCZQ8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=Y5B2LDpqZyyMi23D9/UdIzd EkYs=; b=mDOCBt/T2ENlvXTl7o2ahNY7s96pHcKZrL12ko5p+01MosCWa5QGiLe iSCTUyw7EQulM4mjwtB/A0YzoaijM2AdOEQpQD/wJtBednDaefPyz+Feilx3/IXV VrPoobIEtFRKM2VL6n+/YsxxuDm9m7ZjYYVb8u0yyYbDZWLi4yAY= Received: (qmail 84123 invoked by alias); 6 Dec 2016 11:37:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 84114 invoked by uid 89); 6 Dec 2016 11:37:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=6-branch, 6branch, if_then_else, 2016-11-21 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Dec 2016 11:37:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3713FAD7; Tue, 6 Dec 2016 03:36:59 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6FC8F3F24D; Tue, 6 Dec 2016 03:36:58 -0800 (PST) Subject: Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix ICE when compiling empty FIQ interrupt handler in ARM mode To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> <582C2946.6030900@foss.arm.com> <5326d119-ded9-4cb1-c13b-61f7a0c85f2e@foss.arm.com> From: Thomas Preudhomme Message-ID: <595d0543-5579-7cf7-06b5-032266c1dae0@foss.arm.com> Date: Tue, 6 Dec 2016 11:36:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <5326d119-ded9-4cb1-c13b-61f7a0c85f2e@foss.arm.com> X-IsSubscribed: yes Ping? Best regards, Thomas On 30/11/16 10:20, Thomas Preudhomme wrote: > Hi, > > Is this ok to backport this fix together with its follow-up testcase fix to > gcc-5-branch and gcc-6-branch? Both patches apply cleanly (patches attached for > reference). > > > 2016-11-30 Thomas Preud'homme > > Backport from mainline > 2016-11-16 Thomas Preud'homme > > gcc/ > * config/arm/arm.md (arm_addsi3): Add alternative for addition of > general register with general register or ARM constant into SP > register. > > gcc/testsuite/ > * gcc.target/arm/empty_fiq_handler.c: New test. > > Backport from mainline > 2016-11-21 Thomas Preud'homme > > gcc/testsuite/ > * gcc.target/arm/empty_fiq_handler.c: Skip if -mthumb is passed in and > target is Thumb-only. > > > Best regards, > > Thomas > > > On 16/11/16 09:39, Kyrill Tkachov wrote: >> >> On 09/11/16 16:19, Thomas Preudhomme wrote: >>> Hi, >>> >>> This patch fixes the following ICE when building when compiling an empty FIQ >>> interrupt handler in ARM mode: >>> >>> empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints: >>> } >>> ^ >>> >>> (insn/f 13 12 14 (set (reg/f:SI 13 sp) >>> (plus:SI (reg/f:SI 11 fp) >>> (const_int 4 [0x4]))) irq.c:5 4 {*arm_addsi3} >>> (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp) >>> (plus:SI (reg/f:SI 11 fp) >>> (const_int 4 [0x4]))) >>> (nil))) >>> >>> The ICE was provoked by missing an alternative to reflect that ARM mode can do >>> an add of general register into sp which is unpredictable in Thumb mode add >>> immediate. >>> >>> ChangeLog entries are as follow: >>> >>> *** gcc/ChangeLog *** >>> >>> 2016-11-04 Thomas Preud'homme >>> >>> * config/arm/arm.md (arm_addsi3): Add alternative for addition of >>> general register with general register or ARM constant into SP >>> register. >>> >>> >>> *** gcc/testsuite/ChangeLog *** >>> >>> 2016-11-04 Thomas Preud'homme >>> >>> * gcc.target/arm/empty_fiq_handler.c: New test. >>> >>> >>> Testing: bootstrapped on ARMv7-A ARM mode & testsuite shows no regression. >>> >>> Is this ok for trunk? >>> >> >> I see that "r" does not include the stack pointer (STACK_REG is separate from >> GENERAL_REGs) so we are indeed missing >> that constraint. >> >> Ok for trunk. >> Thanks, >> Kyrill >> >>> Best regards, >>> >>> Thomas >> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 47171b99682207226aa4f9a76d4dfb54d6c2814b..86df1c0366be6c4b9b4ebf76821a8100c4e9fc16 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -575,9 +575,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -587,6 +587,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -606,10 +607,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 0000000000000000000000000000000000000000..8313f2199122be153a737946e817a5e3bee60372 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +}