From patchwork Thu Mar 9 09:15:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 736910 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vf4Vw6MF0z9s7g for ; Thu, 9 Mar 2017 20:15:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="soEtdgVe"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=nWBRVzWpxo+t9ttVx1gCwJL47oq6iookNJI2KIVevTm C5CmoBXVYhNmt1TZlNGH5Y3lP7zMhBH6Vp3hYuHsGyrNZRyq9xkOWzWnfIS8chFZ IPWvL29I9JGzV0ByM8WcwRORfMYMsVJWPKqs2TQuDLv6+AWIk/oM+SsjGkDxhwl0 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=VzK32NvQft7c2r35QLCk/C5KEos=; b=soEtdgVex9jF64gR8 VpJ0xI4SFEBhWw1XXxoAnYI1cqmoN8tCsU17598LcdWdeR+BUJKKaIE0WJ7NTj8I aTc+Ck0jXJTt2onafdjg95dqnazKPs0c28N+kvOt4EjfXf8ZfBQiS5IciPcIZnIz flzGeoa9osI/kiwwLw77ijyL4A= Received: (qmail 29302 invoked by alias); 9 Mar 2017 09:15:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19475 invoked by uid 89); 9 Mar 2017 09:15:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=vel, 778, VEL, Hx-languages-length:5358 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 09 Mar 2017 09:15:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C16B5344; Thu, 9 Mar 2017 01:15:07 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F08A83F3E1; Thu, 9 Mar 2017 01:15:06 -0800 (PST) Message-ID: <58C11D19.30600@foss.arm.com> Date: Thu, 09 Mar 2017 09:15:05 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] PR target/79913: VEC_SELECT bugs in aarch64 patterns Hi all, This patch fixes the vec_select errors found by Jakub's genrecog validation improvements: ../../gcc/config/aarch64/aarch64-simd.md:79:1: DImode of first vec_select operand is not a vector mode ../../gcc/config/aarch64/aarch64-simd.md:79:1: DFmode of first vec_select operand is not a vector mode ../../gcc/config/aarch64/aarch64-simd.md:588:1: DImode of first vec_select operand is not a vector mode ../../gcc/config/aarch64/aarch64-simd.md:588:1: DFmode of first vec_select operand is not a vector mode ../../gcc/config/aarch64/aarch64-simd.md:3192:1: DFmode of first vec_select operand is not a vector mode The first four are in the DUP and INS lane patterns. They iterate over the VALL_F16 or VALL mode iterators that include V2DI and V2DF. The VSWAP_WIDTH attribute for these modes are the scalar DI and DF, which are not valid as modes of a vec_select operand. The problematic patterns deal with lane copies between elements of 64-bit vectors to 128-bit vectors and vice versa. 64 to 64-bit and 128 to 128-bit copies are handled in separate patterns (aarch64_dup_lane and *aarch64_simd_vec_copy_lane). But there is no variant of those instructions to copy a 64-bit element from a 128-bit vector to a 64-bit vector (A DUP V.1D, V.D[0] for example). Similarly, there is no INS instruction to move from a 128-bit vector of 2 64-bit elements to a 64-bit "vector" of one 64-bit element. James also noticed that these patterns don't handle HFmode, so this patch also adds that to their iterator. The last error is the *aarch64_vgetfmulx pattern. It uses the VDQF_DF iterator on the vec_select argument. But VDQF_DF includes DFmode, which is scalar and thus not valid here. I think the best course of action here is to not iterate over DFmode in this pattern. It's not clear what a vec_select was intended to express for that case and there are other patterns that do a fmulx on scalar 64-bit operands. Removing the DFmode from the iterated modes fixes the error and the relevant intrinsics tests run just fine (plus some other more rigorous AdvSIMD intrinsics tests that I run). With these fixes the genrecog validation doesn't complain for aarch64. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk? Thanks, Kyrill 2017-03-09 Kyrylo Tkachov PR target/79913 * config/aarch64/iterators.md (VALL_F16_NO_V2Q): New mode iterator. (VALL_NO_V2Q): Likewise. (VDQF_DF): Delete. * config/aarch64/aarch64-simd.md (aarch64_dup_lane_): Use VALL_F16_NO_V2Q iterator. (*aarch64_simd_vec_copy_lane_): Use VALL_NO_V2Q mode iterator. (*aarch64_vgetfmulx): Use VDQF iterator. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b61f79a..7ad3a76 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -77,8 +77,8 @@ (define_insn "aarch64_dup_lane" ) (define_insn "aarch64_dup_lane_" - [(set (match_operand:VALL_F16 0 "register_operand" "=w") - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w") + (vec_duplicate:VALL_F16_NO_V2Q (vec_select: (match_operand: 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) @@ -586,14 +586,14 @@ (define_insn "*aarch64_simd_vec_copy_lane" ) (define_insn "*aarch64_simd_vec_copy_lane_" - [(set (match_operand:VALL 0 "register_operand" "=w") - (vec_merge:VALL - (vec_duplicate:VALL + [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w") + (vec_merge:VALL_F16_NO_V2Q + (vec_duplicate:VALL_F16_NO_V2Q (vec_select: (match_operand: 3 "register_operand" "w") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) - (match_operand:VALL 1 "register_operand" "0") + (match_operand:VALL_F16_NO_V2Q 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { @@ -3194,7 +3194,7 @@ (define_insn "*aarch64_vgetfmulx" (unspec: [(match_operand: 1 "register_operand" "w") (vec_select: - (match_operand:VDQF_DF 2 "register_operand" "w") + (match_operand:VDQF 2 "register_operand" "w") (parallel [(match_operand:SI 3 "immediate_operand" "i")]))] UNSPEC_FMULX))] "TARGET_SIMD" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index c59d31e..1ddf6ad 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -101,7 +101,6 @@ (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF]) ;; Vector Float modes, and DF. -(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF DF]) @@ -133,6 +132,10 @@ (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V4HF V8HF V2SF V4SF V2DF]) +;; The VALL_F16 modes except the 128-bit 2-element ones. +(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI + V4HF V8HF V2SF V4SF]) + ;; All vector modes barring HF modes, plus DI. (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])