From patchwork Mon Dec 5 17:01:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 702799 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tXWHl6xCnz9s5w for ; Tue, 6 Dec 2016 04:01:23 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RZ4r3rTY"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=C8/XSn7EhkJ4CiSgr PcK/0ZEghiqDObl5JYg/sgFpURcog2ZK3VGxfzZQ4HO21tFSEhRFPwF39FYLIqfB ++vmm2VhwyPulHsAZ58zZjcbaj1XFVqPJAR81LnpuJLnEL6bo51uQbjET0Nd2M+h wLFQgWFREbUILBpt3U3d6yyA3M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=NFn+LOFc13bkLHM1eEC+BeU nDww=; b=RZ4r3rTYf7n1b8W1lqQctO4d+oa37U6a4L4YTTofGoSsc/VZPJ7c1gL GPNYlrqWRNYG0cMAUMkiIawbCpbdvKEgWeb+AQAfnMp9JRJ6kfVft32GHf5Mxx0F ElYLCsBCQnMT671E/oGSci0MjSTWUxcxbRUc8aalzlhN6zQ1+95E= Received: (qmail 51619 invoked by alias); 5 Dec 2016 17:01:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51605 invoked by uid 89); 5 Dec 2016 17:01:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_ASCII_DIVIDERS, KAM_LOTSOFHASH, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=H*f:sk:5845550, H*MI:sk:5845550, H*i:sk:5845550 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Dec 2016 17:01:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54ADBCF6; Mon, 5 Dec 2016 09:01:02 -0800 (PST) Received: from [10.2.206.251] (e107157-lin.cambridge.arm.com [10.2.206.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 036B43F483 for ; Mon, 5 Dec 2016 09:01:01 -0800 (PST) Subject: [arm-embedded][committed][PATCH 6/6] ARM ACLE Coprocessor MCRR and MRRC intrinsics To: gcc-patches@gcc.gnu.org References: <5822F3CB.3040202@arm.com> <5822F692.2060705@arm.com> <5845550E.7060308@arm.com> From: "Andre Vieira (lists)" Message-ID: <58459D4C.4000908@arm.com> Date: Mon, 5 Dec 2016 17:01:00 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <5845550E.7060308@arm.com> X-IsSubscribed: yes On 05/12/16 11:52, Andre Vieira (lists) wrote: > On 09/11/16 10:12, Andre Vieira (lists) wrote: >> Hi, >> >> This patch implements support for the ARM ACLE Coprocessor MCR and MRC >> intrinsics. See below a table mapping the intrinsics to their respective >> instructions: >> >> +-------------------------------------------------------------------+---------------------------------------+ >> | Intrinsic signature | >> Instruction pattern | >> +-------------------------------------------------------------------+---------------------------------------+ >> |void __arm_mcrr(coproc, opc1, uint64_t value, CRm) | >> MCRR coproc, opc1, Rt, Rt2, CRm | >> +-------------------------------------------------------------------+---------------------------------------+ >> |void __arm_mcrr2(coproc, opc1, uint64_t value, CRm) | >> MCRR2 coproc, opc1, Rt, Rt2, CRm | >> +-------------------------------------------------------------------+---------------------------------------+ >> |uint64_t __arm_mrrc(coproc, opc1, CRm) | >> MRRC coproc, opc1, Rt, Rt2, CRm | >> +-------------------------------------------------------------------+---------------------------------------+ >> |uint64_t __arm_mrrc2(coproc, opc1, CRm) | >> MRRC2 coproc, opc1, Rt, Rt2, CRm | >> +-------------------------------------------------------------------+---------------------------------------+ >> Note that any untyped variable in the intrinsic signature is required to >> be a compiler-time constant and has the type 'unsigned int'. We do some >> boundary checks for coproc:[0-15], opc1[0-7] CR*:[0-31]. If either of >> these requirements are not met a diagnostic is issued. >> >> I added a new arm_arch variable for ARMv5TE to use when deciding whether >> or not the MCRR and MRCC intrinsics are available. >> >> Is this OK for trunk? >> >> Regards, >> Andre >> >> gcc/ChangeLog: >> 2016-11-09 Andre Vieira >> >> * config/arm/arm.md (): New. >> (): New. >> * config/arm/arm.c (arm_arch5te): New. >> (arm_option_override): Set arm_arch5te. >> (arm_coproc_builtin_available): Add support for mcrr, mcrr2, mrrc >> and mrrc2. >> * config/arm/arm-builtins.c (MCRR_QUALIFIERS): Define to... >> (arm_mcrr_qualifiers): ... this. New. >> (MRRC_QUALIFIERS): Define to... >> (arm_mrrc_qualifiers): ... this. New. >> * config/arm/arm_acle.h (__arm_mcrr, __arm_mcrr2, __arm_mrrc, >> __arm_mrrc2): New. >> * config/arm/arm_acle_builtins.def (mcrr, mcrr2, mrrc, mrrc2): New. >> * config/arm/iterators.md (MCRRI, mcrr, MCRR): New. >> (MRRCI, mrrc, MRRC): New. >> * config/arm/unspecs.md (VUNSPEC_MCRR, VUNSPEC_MCRR2, VUNSPEC_MRRC, >> VUNSPEC_MRRC2): New. >> >> gcc/testsuite/ChangeLog: >> >> 2016-11-09 Andre Vieira >> >> * gcc.target/arm/acle/mcrr: New. >> * gcc.target/arm/acle/mcrr2: New. >> * gcc.target/arm/acle/mrrc: New. >> * gcc.target/arm/acle/mrrc2: New. >> > Hi, > > I realize I forgot to mention that for these intrinsics 'Rt' will hold > the low half and 'Rt2' the higher half of either the argument 'value' > for MCRR{,2} or the return value for MRRC{,2}. > > Cheers, > Andre > Hi, I committed this patch to the embedded-6-branch in revision r243264. Cheers, Andre gcc/ChangeLog.arm: 2016-12-05 Andre Vieira * config/arm/arm.md (): New. (): New. * config/arm/arm.c (arm_arch5te): New. (arm_option_override): Set arm_arch5te. (arm_coproc_builtin_available): Add support for mcrr, mcrr2, mrrc and mrrc2. * config/arm/arm-builtins.c (MCRR_QUALIFIERS): Define to... (arm_mcrr_qualifiers): ... this. New. (MRRC_QUALIFIERS): Define to... (arm_mrrc_qualifiers): ... this. New. * config/arm/arm_acle.h (__arm_mcrr, __arm_mcrr2, __arm_mrrc, __arm_mrrc2): New. * config/arm/arm_acle_builtins.def (mcrr, mcrr2, mrrc, mrrc2): New. * config/arm/iterators.md (MCRRI, mcrr, MCRR): New. (MRRCI, mrrc, MRRC): New. * config/arm/unspecs.md (VUNSPEC_MCRR, VUNSPEC_MCRR2, VUNSPEC_MRRC, VUNSPEC_MRRC2): New. gcc/testsuite/ChangeLog.arm: 2016-12-05 Andre Vieira * gcc.target/arm/acle/mcrr: New. * gcc.target/arm/acle/mcrr2: New. * gcc.target/arm/acle/mrrc: New. * gcc.target/arm/acle/mrrc2: New. diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm index 3f7d684fd8264d5194d78b04fb237ea28012f714..3ca93cba4ec2f8f62710b2625ce765e234a173a8 100644 --- a/gcc/ChangeLog.arm +++ b/gcc/ChangeLog.arm @@ -1,5 +1,25 @@ 2016-12-05 Andre Vieira + * config/arm/arm.md (): New. + (): New. + * config/arm/arm.c (arm_arch5te): New. + (arm_option_override): Set arm_arch5te. + (arm_coproc_builtin_available): Add support for mcrr, mcrr2, mrrc + and mrrc2. + * config/arm/arm-builtins.c (MCRR_QUALIFIERS): Define to... + (arm_mcrr_qualifiers): ... this. New. + (MRRC_QUALIFIERS): Define to... + (arm_mrrc_qualifiers): ... this. New. + * config/arm/arm_acle.h (__arm_mcrr, __arm_mcrr2, __arm_mrrc, + __arm_mrrc2): New. + * config/arm/arm_acle_builtins.def (mcrr, mcrr2, mrrc, mrrc2): New. + * config/arm/iterators.md (MCRRI, mcrr, MCRR): New. + (MRRCI, mrrc, MRRC): New. + * config/arm/unspecs.md (VUNSPEC_MCRR, VUNSPEC_MCRR2, VUNSPEC_MRRC, + VUNSPEC_MRRC2): New. + +2016-12-05 Andre Vieira + * config/arm/arm.md (): New. (): New. * config/arm/arm.c (arm_coproc_builtin_available): Add diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 6261b046ab7834c218db2ed4c2fa62fccaf05583..f569dd98ac7092248aa91d3ad2aee9921d3d0859 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -215,6 +215,24 @@ arm_mrc_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_unsigned_immediate, qualifier_unsigned_immediate }; #define MRC_QUALIFIERS \ (arm_mrc_qualifiers) + +/* void (unsigned immediate, unsigned immediate, T, unsigned immediate). */ +static enum arm_type_qualifiers +arm_mcrr_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned_immediate, + qualifier_unsigned_immediate, qualifier_none, + qualifier_unsigned_immediate }; +#define MCRR_QUALIFIERS \ + (arm_mcrr_qualifiers) + +/* T (unsigned immediate, unsigned immediate, unsigned immediate). */ +static enum arm_type_qualifiers +arm_mrrc_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned_immediate, + qualifier_unsigned_immediate, qualifier_unsigned_immediate }; +#define MRRC_QUALIFIERS \ + (arm_mrrc_qualifiers) + /* The first argument (return type) of a store should be void type, which we represent with qualifier_void. Their first operand will be a DImode pointer to the location to store to, so we must use diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e716c2e050dca6d54d9fcde7b6e12a875b0586be..45760d4d5eb2e947b7ce10ff60cf6adc38d78bf6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -815,6 +815,9 @@ int arm_arch5 = 0; /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ int arm_arch5e = 0; +/* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ +int arm_arch5te = 0; + /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ int arm_arch6 = 0; @@ -3197,6 +3200,7 @@ arm_option_override (void) arm_arch4t = arm_arch4 && (ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)); arm_arch5 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5); arm_arch5e = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5E); + arm_arch5te = arm_arch5e && ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB); arm_arch6 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6); arm_arch6k = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6K); arm_arch6kz = arm_arch6k && ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6KZ); @@ -31536,6 +31540,15 @@ bool arm_coproc_builtin_available (enum unspecv builtin) if (arm_arch5) return true; break; + case VUNSPEC_MCRR: + case VUNSPEC_MCRR2: + case VUNSPEC_MRRC: + case VUNSPEC_MRRC2: + /* Only present in ARMv5TE, ARMv6 (but not ARMv6-M), ARMv7* and + ARMv8-{A,M}. */ + if (arm_arch6 || arm_arch5te) + return true; + break; default: gcc_unreachable (); } diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7e82d7ee7bac411d399760a4e6b433b9fd82190e..9593d6c744c6de203605f953ded92797d4583733 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11576,6 +11576,37 @@ [(set_attr "length" "4") (set_attr "type" "coproc")]) +(define_insn "" + [(unspec_volatile [(match_operand:SI 0 "immediate_operand") + (match_operand:SI 1 "immediate_operand") + (match_operand:DI 2 "s_register_operand") + (match_operand:SI 3 "immediate_operand")] MCRRI) + (use (match_dup 2))] + "arm_coproc_builtin_available (VUNSPEC_)" +{ + arm_const_bounds (operands[0], 0, 16); + arm_const_bounds (operands[1], 0, 8); + arm_const_bounds (operands[3], 0, (1 << 5)); + return "\\tp%c0, %1, %Q2, %R2, CR%c3"; +} + [(set_attr "length" "4") + (set_attr "type" "coproc")]) + +(define_insn "" + [(set (match_operand:DI 0 "s_register_operand") + (unspec_volatile [(match_operand:SI 1 "immediate_operand") + (match_operand:SI 2 "immediate_operand") + (match_operand:SI 3 "immediate_operand")] MRRCI))] + "arm_coproc_builtin_available (VUNSPEC_)" +{ + arm_const_bounds (operands[1], 0, 16); + arm_const_bounds (operands[2], 0, 8); + arm_const_bounds (operands[3], 0, (1 << 5)); + return "\\tp%c1, %2, %Q0, %R0, CR%c3"; +} + [(set_attr "length" "4") + (set_attr "type" "coproc")]) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h index 2a202f3982176ba8fd7475ee75863034eff662e6..68a5ede0e2eee5e416faf78baefb98776d03e82b 100644 --- a/gcc/config/arm/arm_acle.h +++ b/gcc/config/arm/arm_acle.h @@ -136,6 +136,37 @@ __arm_mrc2 (const unsigned int __coproc, const unsigned int __opc1, { return __builtin_arm_mrc2 (__coproc, __opc1, __CRn, __CRm, __opc2); } + +#if __ARM_ARCH >= 6 || defined (__ARM_ARCH_5TE__) + +__extension__ static __inline void __attribute__ ((__always_inline__)) +__arm_mcrr (const unsigned int __coproc, const unsigned int __opc1, + uint64_t __value, const unsigned int __CRm) +{ + return __builtin_arm_mcrr (__coproc, __opc1, __value, __CRm); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +__arm_mcrr2 (const unsigned int __coproc, const unsigned int __opc1, + uint64_t __value, const unsigned int __CRm) +{ + return __builtin_arm_mcrr2 (__coproc, __opc1, __value, __CRm); +} + +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +__arm_mrrc (const unsigned int __coproc, const unsigned int __opc1, + const unsigned int __CRm) +{ + return __builtin_arm_mrrc (__coproc, __opc1, __CRm); +} + +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +__arm_mrrc2 (const unsigned int __coproc, const unsigned int __opc1, + const unsigned int __CRm) +{ + return __builtin_arm_mrrc2 (__coproc, __opc1, __CRm); +} +#endif /* __ARM_ARCH >= 6 || defined (__ARM_ARCH_5TE__). */ #endif /* __ARM_ARCH >= 5. */ #endif /* (!__thumb__ || __thumb2__) && __ARM_ARCH >= 4. */ diff --git a/gcc/config/arm/arm_acle_builtins.def b/gcc/config/arm/arm_acle_builtins.def index d258f8a3748f6b4f0aeb3d4a28c6d4d79597f69c..bd1f66272c9c9832a74081838ee81be26bd8ee50 100644 --- a/gcc/config/arm/arm_acle_builtins.def +++ b/gcc/config/arm/arm_acle_builtins.def @@ -38,3 +38,7 @@ VAR1 (MCR, mcr, void) VAR1 (MCR, mcr2, void) VAR1 (MRC, mrc, si) VAR1 (MRC, mrc2, si) +VAR1 (MCRR, mcrr, void) +VAR1 (MCRR, mcrr2, void) +VAR1 (MRRC, mrrc, di) +VAR1 (MRRC, mrrc2, di) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 1412660070d9e094e023217af1c2e0d52d7f01a4..23b4293ad5b410c33c18a3e2012d53b816f0b37a 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -879,3 +879,15 @@ (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) + +;; An iterator for the MCRR coprocessor instructions +(define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) + +(define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) +(define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) + +;; An iterator for the MRRC coprocessor instructions +(define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) + +(define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) +(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 406e828ca46f3314db52c9864d180707fb88f6b1..ce725f23e4ae90529b0c1d76568500a7230d4ee2 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -164,6 +164,10 @@ VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction. VUNSPEC_MRC ; Represent the coprocessor mrc instruction. VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction. + VUNSPEC_MCRR ; Represent the coprocessor mcrr instruction. + VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction. + VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction. + VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction. ]) ;; Enumerators for NEON unspecs. diff --git a/gcc/testsuite/ChangeLog.arm b/gcc/testsuite/ChangeLog.arm index 956bac08398965a91348928a39eab0c9e52e0ae1..486ec685018fd28c04bf7afb5abbc6acfa465af2 100644 --- a/gcc/testsuite/ChangeLog.arm +++ b/gcc/testsuite/ChangeLog.arm @@ -1,5 +1,12 @@ 2016-12-05 Andre Vieira + * gcc.target/arm/acle/mcrr: New. + * gcc.target/arm/acle/mcrr2: New. + * gcc.target/arm/acle/mrrc: New. + * gcc.target/arm/acle/mrrc2: New. + +2016-12-05 Andre Vieira + * gcc.target/arm/acle/mcr.c: New. * gcc.target/arm/acle/mrc.c: New. * gcc.target/arm/acle/mcr2.c: New. diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c new file mode 100644 index 0000000000000000000000000000000000000000..dcc223c713d8aabb1d51c1d3bb3a7ed817a4be30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c @@ -0,0 +1,16 @@ +/* Test the mcrr ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps" } */ +/* { dg-require-effective-target arm_coproc3_ok } */ + +#include "arm_acle.h" + +void test_mcrr (uint64_t a) +{ + a += 77; + __arm_mcrr (10, 5, a, 3); +} + +/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */ +/* { dg-final { scan-assembler "mcrr\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c new file mode 100644 index 0000000000000000000000000000000000000000..a341169b123eafcbedd8c9cfaf2b4e00b89f2970 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c @@ -0,0 +1,16 @@ +/* Test the mcrr2 ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps" } */ +/* { dg-require-effective-target arm_coproc3_ok } */ + +#include "arm_acle.h" + +void test_mcrr2 (uint64_t a) +{ + a += 77; + __arm_mcrr2 (10, 5, a, 3); +} + +/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */ +/* { dg-final { scan-assembler "mcrr2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c new file mode 100644 index 0000000000000000000000000000000000000000..28c3b8ea6b53f7e8cf95d86d4d0eda367fca2041 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c @@ -0,0 +1,14 @@ +/* Test the mrrc ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps" } */ +/* { dg-require-effective-target arm_coproc3_ok } */ + +#include "arm_acle.h" + +uint64_t test_mrrc (void) +{ + return __arm_mrrc (10, 5, 3); +} + +/* { dg-final { scan-assembler "mrrc\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c new file mode 100644 index 0000000000000000000000000000000000000000..1e89828e1580b8b483cd0fbc7234b4b2c1d6b1f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c @@ -0,0 +1,14 @@ +/* Test the mrrc2 ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-options "-save-temps" } */ +/* { dg-require-effective-target arm_coproc3_ok } */ + +#include "arm_acle.h" + +uint64_t test_mrrc2 (void) +{ + return __arm_mrrc2 (10, 5, 3); +} + +/* { dg-final { scan-assembler "mrrc2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */