From patchwork Thu Oct 27 08:50:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 687508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4LG8450Yz9t0P for ; Thu, 27 Oct 2016 19:51:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=qNGJElQO; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=mJgCrgywUW6qtqII7WuVEcsLUckSaN3/pNBFyby6GcITYVSOU8qd6 WVf5jFtGrAigFu2pxM9DfPz0zJ0s9BpjX/ZJVumhFGOuS8ysgEiaAsGh0j/Jf4Wh Xfjwtf6bSFZ6y0AvvsyzrlFGkcZ+nMQVPHKdNF8cHObXaV7khM/HVU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; s=default; bh=P6SiilW2yFbb/8fvhzOhBb7Gtw4=; b=qNGJElQOtbsU8XCB/HxZmDO8kdau gM8SDnzPLscLyEbCPxkKQVLz/X4x10xBujuHYMLLLF3KVVg06P2ztvOHkiUaKKX3 1G5ILRzPIo6x2+Sj+Ei+nrs1pDmrGbRcMDv4riJwElklEWtIdS6O3Avce2I5rq2D /SB9OSfQXA+e6xM= Received: (qmail 73754 invoked by alias); 27 Oct 2016 08:51:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73741 invoked by uid 89); 27 Oct 2016 08:51:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=sk:thumb1_, COND, atomic_, Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Oct 2016 08:50:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7479829; Thu, 27 Oct 2016 01:50:50 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A666C3F218; Thu, 27 Oct 2016 01:50:49 -0700 (PDT) Message-ID: <5811BFE8.4030402@foss.arm.com> Date: Thu, 27 Oct 2016 09:50:48 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Thomas Preudhomme , "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan , Richard Earnshaw Subject: Re: [PATCH, ARM 5/7, ping3] Adapt other atomic operations to ARMv8-M Baseline References: <85c67284-58c0-7b7c-3881-9e097dfb427f@foss.arm.com> <79cd1dee-59dd-af3f-c60a-51f8e15ad1c0@foss.arm.com> <83e33d86-1e58-a778-154d-a478e29d3e5f@foss.arm.com> <5370bdb8-0b62-504c-c4f4-a666bb0ea894@foss.arm.com> In-Reply-To: <5370bdb8-0b62-504c-c4f4-a666bb0ea894@foss.arm.com> Hi Thomas, On 24/10/16 09:05, Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On 14/10/16 14:51, Thomas Preudhomme wrote: >> Ping? >> >> Best regards, >> >> Thomas >> >> On 03/10/16 17:45, Thomas Preudhomme wrote: >>> Ping? >>> >>> Best regards, >>> >>> Thomas >>> >>> On 22/09/16 14:47, Thomas Preudhomme wrote: >>>> Hi, >>>> >>>> This patch is part of a patch series to add support for atomic operations on >>>> ARMv8-M Baseline targets in GCC. This specific patch adds support for remaining >>>> atomic operations (exchange, addition, substraction, bitwise AND, OR, XOR and >>>> NAND to ARMv8-M Baseline, doubleword integers excepted. As with the previous >>>> patch in the patch series, this mostly consists adding Thumb-1 specific >>>> constraints to atomic_* patterns to match those in thumb1.md for the non atomic >>>> operation. >>>> >>>> ChangeLog entry is as follows: >>>> >>>> *** gcc/ChangeLog *** >>>> >>>> 2016-09-02 Thomas Preud'homme >>>> >>>> * config/arm/arm.c (arm_split_atomic_op): Add function comment. Add >>>> logic to to decide whether to copy over old value to register for new >>>> value. >>>> * config/arm/sync.md: Add comments explaning why mode and code >>>> attribute are not defined in iterators.md >>>> (thumb1_atomic_op_str): New code attribute. >>>> (thumb1_atomic_newop_str): Likewise. >>>> (thumb1_atomic_fetch_op_str): Likewise. >>>> (thumb1_atomic_fetch_newop_str): Likewise. >>>> (thumb1_atomic_fetch_oldop_str): Likewise. >>>> (atomic_exchange): Add new ARMv8-M Baseline only alternatives to >>>> mirror the more restrictive constraints of the Thumb-1 insns after >>>> split compared to Thumb-2 counterpart insns. >>>> (atomic_): Likewise. Add comment to keep constraints >>>> in sync with non atomic version. >>>> (atomic_nand): Likewise. >>>> (atomic_fetch_): Likewise. >>>> (atomic_fetch_nand): Likewise. >>>> (atomic__fetch): Likewise. >>>> (atomic_nand_fetch): Likewise. >>>> * config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint >>>> in sync with atomic version. >>>> (thumb1_subsi3_insn): Likewise. >>>> (thumb1_andsi3_insn): Likewise. >>>> (thumb1_iorsi3_insn): Likewise. >>>> (thumb1_xorsi3_insn): Likewise. >>>> >>>> >>>> Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all >>>> atomic and synchronization testcases in the testsuite [2]. Patchset was also >>>> bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at >>>> optimization level -O1 and above [1] without any regression in the testsuite and >>>> no code generation difference in libitm and libgomp. >>>> >>>> Code generation for ARMv8-M Baseline has been manually examined and compared >>>> against ARMv8-A Thumb-2 for the following configuration without finding any >>>> issue: >>>> >>>> gcc.dg/atomic-op-2.c at -Os >>>> gcc.dg/atomic-compare-exchange-2.c at -Os >>>> gcc.dg/atomic-compare-exchange-3.c at -O3 >>>> >>>> >>>> Is this ok for trunk? >>>> >>>> Best regards, >>>> >>>> Thomas >>>> >>>> [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and >>>> undefined ("-O2 -g") >>>> [2] The exact list is: >>>> >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-1.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-2.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-3.c >>>> gcc/testsuite/gcc.dg/atomic-fence.c >>>> gcc/testsuite/gcc.dg/atomic-flag.c >>>> gcc/testsuite/gcc.dg/atomic-generic.c >>>> gcc/testsuite/gcc.dg/atomic-generic-aux.c >>>> gcc/testsuite/gcc.dg/atomic-invalid-2.c >>>> gcc/testsuite/gcc.dg/atomic-load-1.c >>>> gcc/testsuite/gcc.dg/atomic-load-2.c >>>> gcc/testsuite/gcc.dg/atomic-load-3.c >>>> gcc/testsuite/gcc.dg/atomic-lockfree.c >>>> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c >>>> gcc/testsuite/gcc.dg/atomic-noinline.c >>>> gcc/testsuite/gcc.dg/atomic-noinline-aux.c >>>> gcc/testsuite/gcc.dg/atomic-op-1.c >>>> gcc/testsuite/gcc.dg/atomic-op-2.c >>>> gcc/testsuite/gcc.dg/atomic-op-3.c >>>> gcc/testsuite/gcc.dg/atomic-op-6.c >>>> gcc/testsuite/gcc.dg/atomic-store-1.c >>>> gcc/testsuite/gcc.dg/atomic-store-2.c >>>> gcc/testsuite/gcc.dg/atomic-store-3.c >>>> gcc/testsuite/g++.dg/ext/atomic-1.C >>>> gcc/testsuite/g++.dg/ext/atomic-2.C >>>> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-acquire.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-char.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-consume.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-int.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-release.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-short.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c >>>> gcc/testsuite/gcc.target/arm/sync-1.c >>>> gcc/testsuite/gcc.target/arm/synchronize.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c >>>> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc void arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, This is ok with that change. Thanks, Kyrill diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9e4ff0191358f9143ee487ecc0cd60eeb91950c8..fb09dcaf5b8bf322afa9c12446983e833e9d7898 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28307,6 +28307,15 @@ arm_split_compare_and_swap (rtx operands[]) emit_label (label2); } +/* Split an atomic operation pattern. Operation is given by MODE and is one + of PLUS, MINUS, IOR, XOR, SET (for an exchange operation) or NOT (for a nand s/MODE/CODE/. + operation). Operation is performed on the content at MEM and on VALUE + following the memory model MODEL_RTX. The content at MEM before and after + the operation is returned in OLD_OUT and NEW_OUT respectively while the + success of the operation is returned in COND. Using a scratch register or + an operand register for these determines what result is returned for that + pattern. */ +