From patchwork Thu Apr 21 08:15:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 613012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qrBQS1Lm9z9snk for ; Thu, 21 Apr 2016 18:15:43 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=SV1gZrmw; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=QlGyMH9Dl+EICI42ITp9mfwerTWsDbbcI3gTug2ykYp oOK7ibKOfIHdZXOH/fPJ6V3r7Yx+LyF5RIXh1GSXiKu1Pb2EGTn+vk15Urrpd49X saP1T+9OjSuIhTc6CPYcJojlfN6BF7AVTeWHJjH8tQ4QAkEfRZRyPneCmpWtghCA = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=b51xW2oeMDtje2rlWYiBX8sx7/M=; b=SV1gZrmwSK6VD8+XU gBo0yYl4FOyk6aW2/s4qiVQ/VpBfBcgZbpL1vW8oC22TSI4jrI2mfRU9pqlvAL3c j2sozaFmdFv6D+rjuVz/ibmUISbjWwdPJXF5BVRFXbXxsJr6Nu9nyP8+n5ZBmUld p/D73JRFCESmHbuldxZRTd3dzY= Received: (qmail 24538 invoked by alias); 21 Apr 2016 08:15:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 24510 invoked by uid 89); 21 Apr 2016 08:15:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Samsung, tuning, lse, Improvements X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 21 Apr 2016 08:15:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 851A149; Thu, 21 Apr 2016 01:14:03 -0700 (PDT) Received: from [10.2.206.43] (e100706-lin.cambridge.arm.com [10.2.206.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 637BD3F218; Thu, 21 Apr 2016 01:15:19 -0700 (PDT) Message-ID: <57188C15.7030204@foss.arm.com> Date: Thu, 21 Apr 2016 09:15:17 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Jim Wilson , "gerald@pfeifer.com" Subject: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6 Hi all, Here's a proposed summary of the changes in the AArch64 backend for GCC 6. If there's anything I've missed it's purely my oversight, feel free to add entries or suggest improvements. Jim, you added support for the qdf24xx identifier to -mcpu and -mtune. Could you please suggest an appropriate entry to describe it? I think the same format as the Cortex-A35 entry in this patch would be appropriate. Ok to commit? Thanks, Kyrill Index: htdocs/gcc-6/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v retrieving revision 1.62 diff -U 3 -r1.62 changes.html --- htdocs/gcc-6/changes.html 24 Feb 2016 09:36:06 -0000 1.62 +++ htdocs/gcc-6/changes.html 12 Apr 2016 12:47:30 -0000 @@ -312,29 +312,91 @@

AArch64

  • + A number of AArch64-specific options were added. The most important + ones are summarised in this section but for usage instructions please + refer to the documentation. +
    • +
  • The new command line options -march=native, -mcpu=native and -mtune=native are now available on native AArch64 GNU/Linux systems. Specifying these options will cause GCC to auto-detect the host CPU and rewrite these options to the optimal setting for that system. - If GCC is unable to detect the host CPU these options have no effect.
  • - -fpic is now supported by the AArch64 target when generating + -fpic is now supported when generating code for the small code model (-mcmodel=small). The size of the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI , and 15KiB under the ILP32 SysV ABI.
  • - The AArch64 port now supports target attributes and pragmas. Please - refer to the - documentation for details of available attributes and + Target attributes and pragmas are now supported. Please + refer to the documentation for details of available attributes and pragmas as well as usage instructions.
  • Link-time optimization across translation units with different target-specific options is now supported.
    • +
  • + The option -mtls-size= is now supported. It can be used to + specify the bit size of TLS offsets, allowing GCC to generate + better TLS instruction sequences. +
    • +
  • + The option -fno-plt is now fixed and is fully + functional. +
    • +
  • + The ARMv8.1-A architecture and the Large System Extensions are now + supported. They can be used by specifying the + -march=armv8.1-a option. Additionally, the + +lse option extension can be used in a similar fashion + to other option extensions. + The Large System Extensions introduce new instructions that are used + in the implementation of common atomic operations. +
    • +
  • + The ACLE half-precision floating-point type __fp16 is now + supported in the C and C++ languages. +
    • +
  • + The ARM Cortex-A35 processor is now supported via the + -mcpu=cortex-a35 and -mtune=cortex-a35 + options as well as the equivalent target attributes and pragmas. +
    • +
  • + Code generation for the ARM Cortex-A57 processor is improved. + Among general code generation improvements, a better algorithm is + added for allocating registers to floating-point multiply-accumulate + instructions offering increased performance when compiling with + -mcpu=cortex-a57 or -mtune=cortex-a57. +
    • +
  • Code generation for the ARM Cortex-A53 processor is improved. + A more accurate instruction scheduling model for the processor is + now used, and a number of compiler tuning parameters have been set + to offer increased performance when compiling with + -mcpu=cortex-a53 or -mtune=cortex-a53. +
    • +
  • Code generation for the Samsung Exynos M1 processor is improved. + A more accurate instruction scheduling model for the processor is + now used, and a number of compiler tuning parameters have been set + to offer increased performance when compiling with + -mcpu=exynos-m1 or -mtune=exynos-m1. +
    • +
  • + Improvements in the generation of conditional branches and literal + pools were made to allow the compiler to compile functions of a large + size. Constant pools are now placed into separate rodata sections. + The new option -mpc-relative-literal-loads is + introduced to generate per-function literal pools, limiting the maximum + size of functions to 1MiB. +
    • +
  • + Several correctness issues with generation of Advanced SIMD instructions + for big-endian targets have been fixed resulting in improved code + generation for ACLE intrinsics with -mbig-endian. +

ARM