From patchwork Thu Mar 31 16:26:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 604209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qbVK70mYbz9sBc for ; Fri, 1 Apr 2016 03:27:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=brWMDf/o; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=W8Tgf1Q2xZJQsCbYv DEK/dQp3pZ4BWDcmDriXH4mLiKnS/h5e2noY129R69R+uB00aU5MDEXXIsv7nLAq ByQCszNsI41Ebpz72ICV9P5PFLwwLAzqOWWa6yjV0E6ae5WzKOyYeKMpKFlMoHEz Aoz1sDykg+FB/sgusRzr8w59IE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=MjelvcvgA+EjTL+t0Cygam4 QC7o=; b=brWMDf/oTCZL4vgsbcoGeqW/jPsr1K1QuwkAVvMC2IL0VIWpxSq2Bm9 bpu5ro5KEs46/UXxp6X5fr6CFE/SyZqMrMGPbsAAZ7TdSObeJXrSAnVPkojtUWEc ou9iTEXsDftwTLbTVjuPuY5pwbXkhhi08Pp6KBWxBJizubZQervk= Received: (qmail 130684 invoked by alias); 31 Mar 2016 16:26:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130673 invoked by uid 89); 31 Mar 2016 16:26:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 31 Mar 2016 16:26:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6004A3C; Thu, 31 Mar 2016 09:25:36 -0700 (PDT) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8721B3F459; Thu, 31 Mar 2016 09:26:43 -0700 (PDT) Message-ID: <56FD4FC1.70408@foss.arm.com> Date: Thu, 31 Mar 2016 17:26:41 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christophe Lyon , Ramana Radhakrishnan CC: GCC Patches , Ramana Radhakrishnan , Richard Earnshaw Subject: Re: [PATCH][ARM][4.9 Backport] PR target/69875 Fix atomic_loaddi expansion References: <56CD92C2.2090500@foss.arm.com> <56FB8F8F.1000909@foss.arm.com> In-Reply-To: <56FB8F8F.1000909@foss.arm.com> On 30/03/16 09:34, Kyrill Tkachov wrote: > > On 29/03/16 19:46, Christophe Lyon wrote: >> On 16 March 2016 at 16:54, Ramana Radhakrishnan >> wrote: >>> On Wed, Feb 24, 2016 at 11:23 AM, Kyrill Tkachov >>> wrote: >>>> Hi all, >>>> >>>> This is the GCC 4.9 backport of >>>> https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01338.html. >>>> The differences are that TARGET_HAVE_LPAE has to be defined in arm.h in a >>>> different way because >>>> the ARM_FSET_HAS_CPU1 mechanism doesn't exist on this branch. Also, due to >>>> the location of insn_flags >>>> and the various FL_* (on the 4.9 branch they're defined locally in arm.c >>>> rather than in arm-protos.h) >>>> I chose to define TARGET_HAVE_LPAE in terms of hardware divide instruction >>>> availability. This should be >>>> an equivalent definition. >>>> >>>> Also, the scan-assembler tests that check for the DMB instruction are >>>> updated to check for >>>> "dmb sy" rather than "dmb ish", because the memory barrier instruction >>>> changed on trunk for GCC 6. >>>> >>>> Bootstrapped and tested on the GCC 4.9 branch on arm-none-linux-gnueabihf. >>>> >>>> >>>> Ok for the branch after the trunk patch has had a few days to bake? >>> >>> OK. >>> >> Hi Kyrylo, >> >> Since you backported this to branches 4.9 and 5, I've noticed cross-GCC build >> failures: >> --target arm-none-linux-gnueabihf >> --with-mode=arm >> --with-cpu=cortex-a57 >> --with-fpu=crypto-neon-fp-armv8 >> >> The build succeeds --with-mode=thumb. >> >> The error message I'm seeing is: >> /tmp/6190285_22.tmpdir/ccuX17sh.s: Assembler messages: >> /tmp/6190285_22.tmpdir/ccuX17sh.s:34: Error: bad instruction `ldrdeq r0,r1,[r0]' >> make[4]: *** [load_8_.lo] Error 1 >> >> while building libatomic > > Darn, I had re-tested before committing with --with-mode=thumb :( > The problem here is that GCC 5 and 4.9 don't use unified syntax > for arm state (it was switched on for GCC 6), so the output template > in the new arm_atomic_loaddi2_ldrd pattern should be "ldr%(d%)" instead > of "ldrd%?". > > I'll prepare a patch. > Thanks for catching this, > Kyrill > And here it is. I've reproduced the build failure on 4.9 and 5 and confirmed that this patch fixes them and that a build with --with-mode=thumb is unaffected. I'm committing this as obvious in order to fix the broken build in the affected configurations. Sorry for the trouble. Kyrill 2016-03-31 Kyrylo Tkachov * config/arm/sync.md (arm_atomic_loaddi2_ldrd): Fix output template for non-unified syntax. 2016-03-31 Kyrylo Tkachov * gcc.target/arm/atomic_loaddi_relaxed_cond.c: New test. > >> Christophe >> >> >>> Ramana >>>> Thanks, >>>> Kyrill >>>> >>>> 2016-02-24 Kyrylo Tkachov >>>> >>>> PR target/69875 >>>> * config/arm/arm.h (TARGET_HAVE_LPAE): Define. >>>> * config/arm/unspecs.md (VUNSPEC_LDRD_ATOMIC): New value. >>>> * config/arm/sync.md (arm_atomic_loaddi2_ldrd): New pattern. >>>> (atomic_loaddi_1): Delete. >>>> (atomic_loaddi): Rewrite expander using the above changes. >>>> >>>> 2016-02-24 Kyrylo Tkachov >>>> >>>> PR target/69875 >>>> * gcc.target/arm/atomic_loaddi_acquire.x: New file. >>>> * gcc.target/arm/atomic_loaddi_relaxed.x: Likewise. >>>> * gcc.target/arm/atomic_loaddi_seq_cst.x: Likewise. >>>> * gcc.target/arm/atomic_loaddi_1.c: New test. >>>> * gcc.target/arm/atomic_loaddi_2.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_3.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_4.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_5.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_6.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_7.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_8.c: Likewise. >>>> * gcc.target/arm/atomic_loaddi_9.c: Likewise. > diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index acafd0a6ec474466ff7e2c67ae16d9a0dbb9cf5c..17eab93d55c00fd8db3f612bed1caf0e29335f27 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -107,7 +107,7 @@ (define_insn "arm_atomic_loaddi2_ldrd" [(match_operand:DI 1 "arm_sync_memory_operand" "Q")] VUNSPEC_LDRD_ATOMIC))] "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE" - "ldrd%?\t%0, %H0, %C1" + "ldr%(d%)\t%0, %H0, %C1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c new file mode 100644 index 0000000000000000000000000000000000000000..d69775150813a01b7fcab64deac218a6b2c33c56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-add-options arm_arch_v8a } */ + +/* Check that if we conditionalise the atomic load we put the condition + code in the right place to create valid assembly. */ + +#include + +atomic_ullong foo; +int glob; + +int +main (int argc, char *argv[]) +{ + if (argc > 2) + atomic_load_explicit (&foo, memory_order_relaxed); + return glob; +}