From patchwork Wed Mar 9 12:56:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 595057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7AFC91402DE for ; Wed, 9 Mar 2016 23:56:43 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=ywuQXW3o; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=pqh7PyQpKAWRR0S8rZ7CcsP4s0ob2GKFkw41SWBuujH 8Bxyrx+JE9Vtb7EhCMQLgUZP4Osae7Bz1XqCDFWP46Rs9LWbzoVmSwDHMei6aYhR DE8uLNLeS7p51qo8gY9ZhaYdUlh0trGGFfodDvXTpogv8DNLZq8XtUh0vBTvNozk = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=6GyIVDgovQVzSSyA7qnsG2ePUXM=; b=ywuQXW3o3hOgkbER/ tX7a9B8A1UeYshqXJSg3WZHPCQ35upGWuzHCgJUmn3StoZBtUZ0zFKUNN6hV+fN4 +loetpA4EfYQMwGgt2QHgt01k3cUTQh54FnHG7wmFc3VV9N6MtY7wv2mcaeb41QP 7EBlP4IGcK6W6XyhGA+eWXDllo= Received: (qmail 61140 invoked by alias); 9 Mar 2016 12:56:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61127 invoked by uid 89); 9 Mar 2016 12:56:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=match_dup, MODE, strex, outofbounds X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 09 Mar 2016 12:56:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38EB749; Wed, 9 Mar 2016 04:55:25 -0800 (PST) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0AB663F246; Wed, 9 Mar 2016 04:56:22 -0800 (PST) Message-ID: <56E01D75.40807@foss.arm.com> Date: Wed, 09 Mar 2016 12:56:21 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] Use proper output modifier for DImode register in store exclusive patterns Hi all, I notice that the output code for our store exclusive patterns accesses unallocated memory. It wants to output an strexd instruction with a pair of consecutive registers corresponding to a DImode value. For that it creates the SImode top half of the DImode register and puts it into operands[3]. But the pattern only defines entries only up to operands[2], with no match_dup 3 or like that, so operands[3] should technically be out of bounds. We already have a mechanism for printing the top half of a DImode register, that's the 'H' output modifier. So this patch changes those patterns to use that, eliminating the out of bounds access and making the code a bit simpler as well. Bootstrapped and tested on arm-none-linux-gnueabihf. Ok for trunk? Thanks, Kyrill 2016-03-09 Kyrylo Tkachov * config/arm/sync.md (arm_store_exclusive): Use 'H' output modifier on operands[2] rather than creating a new entry in out-of-bounds memory of the operands array. (arm_store_release_exclusivedi): Likewise. diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 6dd2dc396210bc45374d13e1a20f124cc490b630..8158f53025400045569533a1e8c6583025d490c8 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -422,14 +422,13 @@ (define_insn "arm_store_exclusive" { if (mode == DImode) { - rtx value = operands[2]; /* The restrictions on target registers in ARM mode are that the two registers are consecutive and the first one is even; Thumb is actually more flexible, but DI should give us this anyway. - Note that the 1st register always gets the lowest word in memory. */ - gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); - operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); - return "strexd%?\t%0, %2, %3, %C1"; + Note that the 1st register always gets the + lowest word in memory. */ + gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); + return "strexd%?\t%0, %2, %H2, %C1"; } return "strex%?\t%0, %2, %C1"; } @@ -445,11 +444,9 @@ (define_insn "arm_store_release_exclusivedi" VUNSPEC_SLX))] "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" { - rtx value = operands[2]; /* See comment in arm_store_exclusive above. */ - gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); - operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); - return "stlexd%?\t%0, %2, %3, %C1"; + gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); + return "stlexd%?\t%0, %2, %H2, %C1"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")])