diff mbox

[ARM] PR target/69161: Don't ignore mode when matching comparison operator in cstore-like patterns

Message ID 56C47835.8030909@foss.arm.com
State New
Headers show

Commit Message

Kyrill Tkachov Feb. 17, 2016, 1:40 p.m. UTC 
Hi Nick,

On 17/02/16 13:13, Nick Clifton wrote:
> Hi Kyrill,
>
>> Ok for trunk?
>>
>> 2016-01-29  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>      PR target/69161
>>      * config/arm/predicates.md (arm_comparison_operator_mode):
>>      New predicate.
>>      * config/arm/arm.md (*mov_scc): Use arm_comparison_operator_mode
>>      instead of arm_comparison_operator.
>>      (*mov_negscc): Likewise.
>>      (*mov_notscc): Likewise.
>>      * config/arm/thumb2.md (*thumb2_mov_scc): Likewise.
>>      (*thumb2_mov_negscc): Likewise.
>>      (*thumb2_mov_negscc_strict_it): Likewise.
>>      (*thumb2_mov_notscc): Likewise.
>>      (*thumb2_mov_notscc_strict_it): Likewise.
> Approved - please apply - but ...
>

Thanks!

>> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
>> index c66c31d5c6047aa7decfe7e95d111d5fbf6fb52e..b8f09ab6b109f80abe2df08a8b7f954f521ec1bf 100644
>> --- a/gcc/config/arm/predicates.md
>> +++ b/gcc/config/arm/predicates.md
>> @@ -341,6 +341,11 @@ (define_special_predicate "arm_comparison_operator"
>>     (and (match_operand 0 "expandable_comparison_operator")
>>          (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
>>   
>> +;; Likewise, but don't ignore the mode.
>> +(define_predicate "arm_comparison_operator_mode"
> Please could you extend the comment here to reference the PR.  That way
> anyone reading this code who wonders why we need to have two versions of
> the same predicate will be able understand what is happening.

Ok, here's what I committed with r233495.

Kyrill

> Cheers
>    Nick
>
diff mbox

Patch

commit 59380f7f3e34f4c4e17a610e67341a0de0272c15
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Jan 13 13:29:36 2016 +0000

    [ARM] PR target/69161: Don't ignore mode when matching comparison operator in cstore patterns

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5129e85..15b4a4a 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7190,7 +7190,7 @@  (define_expand "cstore_cc"
 
 (define_insn_and_split "*mov_scc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(match_operator:SI 1 "arm_comparison_operator"
+	(match_operator:SI 1 "arm_comparison_operator_mode"
 	 [(match_operand 2 "cc_register" "") (const_int 0)]))]
   "TARGET_ARM"
   "#"   ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
@@ -7207,7 +7207,7 @@  (define_insn_and_split "*mov_scc"
 
 (define_insn_and_split "*mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(neg:SI (match_operator:SI 1 "arm_comparison_operator"
+	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_ARM"
   "#"   ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index c66c31d..f696458 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -341,6 +341,13 @@  (define_special_predicate "arm_comparison_operator"
   (and (match_operand 0 "expandable_comparison_operator")
        (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
 
+;; Likewise, but don't ignore the mode.
+;; RTL SET operations require their operands source and destination have
+;; the same modes, so we can't ignore the modes there.  See PR target/69161.
+(define_predicate "arm_comparison_operator_mode"
+  (and (match_operand 0 "expandable_comparison_operator")
+       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+
 (define_special_predicate "lt_ge_comparison_operator"
   (match_code "lt,ge"))
 
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 39a3d80..9925365 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -370,7 +370,7 @@  (define_insn "*thumb2_cmpsi_neg_shiftsi"
 
 (define_insn_and_split "*thumb2_mov_scc"
   [(set (match_operand:SI 0 "s_register_operand" "=l,r")
-	(match_operator:SI 1 "arm_comparison_operator"
+	(match_operator:SI 1 "arm_comparison_operator_mode"
 	 [(match_operand 2 "cc_register" "") (const_int 0)]))]
   "TARGET_THUMB2"
   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
@@ -388,7 +388,7 @@  (define_insn_and_split "*thumb2_mov_scc"
 
 (define_insn_and_split "*thumb2_mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(neg:SI (match_operator:SI 1 "arm_comparison_operator"
+	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && !arm_restrict_it"
   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
@@ -407,7 +407,7 @@  (define_insn_and_split "*thumb2_mov_negscc"
 
 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
-	(neg:SI (match_operator:SI 1 "arm_comparison_operator"
+	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && arm_restrict_it"
   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
@@ -436,7 +436,7 @@  (define_insn_and_split "*thumb2_mov_negscc_strict_it"
 
 (define_insn_and_split "*thumb2_mov_notscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(not:SI (match_operator:SI 1 "arm_comparison_operator"
+	(not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && !arm_restrict_it"
   "#"   ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
@@ -456,7 +456,7 @@  (define_insn_and_split "*thumb2_mov_notscc"
 
 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
-        (not:SI (match_operator:SI 1 "arm_comparison_operator"
+	(not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && arm_restrict_it"
   "#"   ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"