From patchwork Fri Dec 18 14:29:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 558894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8AC931400A0 for ; Sat, 19 Dec 2015 01:29:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=TH0uuhOR; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=RT0MBARBffexfPzWX50DMSUrAUv6LlMOyEWvzCN+Yqr ymXii+Vf6EKS0usLKHbB3THtdPzFjAVc+I/Zcl+mWVGIW3iuKXSPCRZSfuvaLDGg 5S6TeXTNMqtcP6H+UYSnqgkbqmsTtyav7xC5jJWSDJv2KHmYHV63xtQ5RhOSS0O8 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=PAPd5oXSyGcrSx2v953RWmE+iDI=; b=TH0uuhORjlcZddKQM S38m66NnlK9QeTwedugboV9+REoxUrHP/iV7WLDMilPq2zxiXCEuu5C2cXeLvXXK ha5z27GejuJhq04Vc6U0YVQnAgO6+lRVum2N7x5ig50/1+NI3KTr4jEOUGVMHxyI /ggQWJPTBZ44+vhn8SVevX2C6o= Received: (qmail 65092 invoked by alias); 18 Dec 2015 14:29:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65076 invoked by uid 89); 18 Dec 2015 14:29:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=H*u:31.2.0, H*UA:31.2.0, rtx_equal_p, canonicalise X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Dec 2015 14:29:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA37F5D4; Fri, 18 Dec 2015 06:29:03 -0800 (PST) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 527D03F24D; Fri, 18 Dec 2015 06:29:28 -0800 (PST) Message-ID: <56741846.60708@foss.arm.com> Date: Fri, 18 Dec 2015 14:29:26 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Segher Boessenkool , Bernd Schmidt , Jeff Law Subject: [PATCH][combine][v2] Canonicalise (r + r) to (r << 1) to aid recognition Hi all, Following up from https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01723.html here is the patch that makes combine canonicalise x + x expressions into x << 1. This allows for more simplification opportunities, as well as increases the recognition opportunities on targets that support combined arithmetic and shift instructions, like aarch64 and arm. This has the same effect on aarch64 as my first attempt, i.e. it increases the combination opportunities for -mcpu=cortex-a53 with the added effect that simple register adds of the form: "add x1, x0, x0" are now transformed into shifts "lsl x1, x0, #1". It has been suggested in that thread that if the target wants to distinguish between a shift-by-one and the plus form then it should match the shift form and explicitly output the instruction pattern for the plus form. This would be, of course, a separate aarch64-specific patch. Bootstrapped and tested on arm, aarch64, x86_64. As before, there were no codegen differences for SPEC2006 on x86_64. aarch64 SPEC2006 sees the effects described above. How does this approach look? 2015-12-18 Kyrylo Tkachov PR rtl-optimization/68651 * combine.c (combine_simplify_rtx): Canonicalize x + x into x << 1. 2015-12-18 Kyrylo Tkachov PR rtl-optimization/68651 * gcc.target/aarch64/pr68651_1.c: New test. diff --git a/gcc/combine.c b/gcc/combine.c index 64d334e0b2a6d731310e67779ad3fd74c326a186..dc0d4bd52c717b88608d21dbaffe444eeb68bb2d 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -5897,6 +5897,13 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest, || XEXP (temp, 1) != XEXP (x, 0))))) return temp; } + + /* Canonicalize x + x into x << 1. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && rtx_equal_p (XEXP (x, 0), XEXP (x, 1)) + && !side_effects_p (XEXP (x, 0))) + return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx); + break; case MINUS: diff --git a/gcc/testsuite/gcc.target/aarch64/pr68651_1.c b/gcc/testsuite/gcc.target/aarch64/pr68651_1.c new file mode 100644 index 0000000000000000000000000000000000000000..ef9456f538776e7db01ecf5473425aed9efd9de2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68651_1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a53" } */ + +int +foo (int x) +{ + return (x * 2) & 65535; +} +/* { dg-final { scan-assembler "ubfiz\tw\[0-9\]*, w\[0-9\]*.*\n" } } */ + +int +bar (int x, int y) +{ + return (x * 2) | y; +} +/* { dg-final { scan-assembler "orr\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*, lsl 1.*\n" } } */