From patchwork Fri Oct 30 04:10:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 538114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3D6E31412DD for ; Fri, 30 Oct 2015 15:11:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=CUnB3mtb; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=P61bGj7xkdln+KI9g Cuuon3z2Rjl8G4PY+dhBENSgz9Tdib1vidKhvOimki7kPF861mSaOSyZh7oz0lBR +W9/TQTNF4XpVvMuBRzzWoFT/z9yDlO4QvT6EQloMcVFtKGicbSkLWqJiX04dIjI LYZ77znYq47wieoXTGw3Q20hBA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=X9s2zNhSqMfUqPLWtTISnep IrnA=; b=CUnB3mtbK8dghvDxGiUFvWDV8uQNH4iv+V8E8+mZ3ay4nlOUwmPLMVB 8MGPvYe/W47iEvuvJx7gbb+zzWb5oCk1Zeoy6HFwtzm0f99mz7EnaoOILlkWAOsW hXdpv9xaOodrbMCggtTowWkrpKHpNakbNYK6IYIg7XBIv3Z9FiXE= Received: (qmail 63670 invoked by alias); 30 Oct 2015 04:11:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63660 invoked by uid 89); 30 Oct 2015 04:11:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 30 Oct 2015 04:11:01 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id C166819CB93; Fri, 30 Oct 2015 04:10:59 +0000 (UTC) Received: from localhost.localdomain (ovpn-113-196.phx2.redhat.com [10.3.113.196]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t9U4Ax5B030882; Fri, 30 Oct 2015 00:10:59 -0400 Subject: Re: [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific parts To: Mikhail Maltsev , gcc-patches mailing list , Richard Biener References: <56130763.4070206@gmail.com> <56130A77.4030108@gmail.com> From: Jeff Law Message-ID: <5632EDD2.7020406@redhat.com> Date: Thu, 29 Oct 2015 22:10:58 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <56130A77.4030108@gmail.com> X-IsSubscribed: yes On 10/05/2015 05:40 PM, Mikhail Maltsev wrote: > gcc/ChangeLog: > > 2015-10-05 Mikhail Maltsev > > * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert. > * config/arm/arm.c (arm_unwind_emit_sequence): Adjust to use CHECKING_P. > * config/bfin/bfin.c (hwloop_optimize): Likewise. > * config/i386/i386.c (ix86_print_operand_address, > output_387_binary_op): Likewise. > * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. > * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. > * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): > Likewise. > * config/rs6000/rs6000.h: Likewise. > * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. > Thanks. I've removed most of the inconsistencies Bernd pointed out. I left one bit in ia64.c as I'd like to do a deeper test on removal of that conditional compilation. I bootstrapped and regression tested this patch on x86_64-linux-gnu as building config-list.mk. I'm installing this patch on the trunk. For reference, you'll find the actual patch committed attached to this message, as well as one created ignoring whitespace changes which shows the real changes more clearly. Jeff commit 1d674b45031bb4650ef80a91ac1956764a4ab271 Author: law Date: Fri Oct 30 04:08:15 2015 +0000 [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific parts * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, flag_checking and/or CHECKING_P to eliminate conditional compilation on ENABLE_CHECKING. * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. * config/bfin/bfin.c (hwloop_optimize): Likewise. * config/i386/i386.c (ix86_print_operand_address): Likewise. (output_387_binary_op): Likewise. * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): Likewise. * config/rs6000/rs6000.h: Likewise. * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229567 138bc75d-0d04-0410-961f-82ee72b054a4 commit 1d674b45031bb4650ef80a91ac1956764a4ab271 Author: law Date: Fri Oct 30 04:08:15 2015 +0000 [PATCH 8/9] ENABLE_CHECKING refactoring: target-specific parts * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, flag_checking and/or CHECKING_P to eliminate conditional compilation on ENABLE_CHECKING. * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. * config/bfin/bfin.c (hwloop_optimize): Likewise. * config/i386/i386.c (ix86_print_operand_address): Likewise. (output_387_binary_op): Likewise. * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): Likewise. * config/rs6000/rs6000.h: Likewise. * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229567 138bc75d-0d04-0410-961f-82ee72b054a4 diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9250b6..934711b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2015-10-29 Mikhail Maltsev + + * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, + flag_checking and/or CHECKING_P to eliminate conditional compilation + on ENABLE_CHECKING. + * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. + * config/bfin/bfin.c (hwloop_optimize): Likewise. + * config/i386/i386.c (ix86_print_operand_address): Likewise. + (output_387_binary_op): Likewise. + * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. + * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. + * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): + Likewise. + * config/rs6000/rs6000.h: Likewise. + * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. + 2015-10-29 Kaz Kojima * config/sh/sh.opt (mfdpic): Add missing period. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index d22bf67..11da372 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -5558,11 +5558,9 @@ alpha_function_arg (cumulative_args_t cum_v, machine_mode mode, basereg = 16; else { -#ifdef ENABLE_CHECKING /* With alpha_split_complex_arg, we shouldn't see any raw complex values here. */ - gcc_assert (!COMPLEX_MODE_P (mode)); -#endif + gcc_checking_assert (!COMPLEX_MODE_P (mode)); /* Set up defaults for FP operands passed in FP registers, and integral operands passed in integer registers. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a598c84..7c72a81 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -26857,7 +26857,8 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) else asm_fprintf (asm_out_file, "%r", reg); -#ifdef ENABLE_CHECKING + if (flag_checking) + { /* Check that the addresses are consecutive. */ e = XEXP (SET_DEST (e), 0); if (GET_CODE (e) == PLUS) @@ -26870,7 +26871,7 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) && REG_P (e) && REGNO (e) == SP_REGNUM); offset += reg_size; -#endif + } } fprintf (asm_out_file, "}\n"); if (padfirst) diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 7334a52..6a5f90a 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -3792,8 +3792,7 @@ hwloop_optimize (hwloop_info loop) edge e; edge_iterator ei; -#ifdef ENABLE_CHECKING - if (loop->head != loop->incoming_dest) + if (flag_checking && loop->head != loop->incoming_dest) { /* We aren't entering the loop at the top. Since we've established that the loop is entered only at one point, this means there @@ -3803,7 +3802,6 @@ hwloop_optimize (hwloop_info loop) FOR_EACH_EDGE (e, ei, loop->head->preds) gcc_assert (!(e->flags & EDGE_FALLTHRU)); } -#endif emit_insn_before (seq, BB_HEAD (loop->head)); seq = emit_label_before (gen_label_rtx (), seq); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8476677..913dc00 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -17348,7 +17348,8 @@ ix86_print_operand_address (FILE *file, rtx addr) /* Print SImode register names to force addr32 prefix. */ if (SImode_address_operand (addr, VOIDmode)) { -#ifdef ENABLE_CHECKING + if (flag_checking) + { gcc_assert (TARGET_64BIT); switch (GET_CODE (addr)) { @@ -17363,7 +17364,7 @@ ix86_print_operand_address (FILE *file, rtx addr) default: gcc_unreachable (); } -#endif + } gcc_assert (!code); code = 'k'; } @@ -17620,10 +17621,10 @@ output_387_binary_op (rtx insn, rtx *operands) const char *ssep; int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]); -#ifdef ENABLE_CHECKING /* Even if we do not want to check the inputs, this documents input constraints. Which helps in understanding the following code. */ - if (STACK_REG_P (operands[0]) + if (flag_checking + && STACK_REG_P (operands[0]) && ((REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]) && (STACK_REG_P (operands[2]) || MEM_P (operands[2]))) @@ -17633,8 +17634,7 @@ output_387_binary_op (rtx insn, rtx *operands) && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2]))) ; /* ok */ else - gcc_assert (is_sse); -#endif + gcc_checking_assert (is_sse); switch (GET_CODE (operands[3])) { diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 8791138..d92af17 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6125,7 +6125,7 @@ struct reg_write_state /* Cumulative info for the current instruction group. */ struct reg_write_state rws_sum[NUM_REGS]; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Bitmap whether a register has been written in the current insn. */ HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) / HOST_BITS_PER_WIDEST_FAST_INT]; @@ -7293,15 +7293,13 @@ ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int max_ready ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING - rtx_insn *insn; - - if (!sel_sched_p () && reload_completed) - for (insn = NEXT_INSN (current_sched_info->prev_head); + if (flag_checking && !sel_sched_p () && reload_completed) + { + for (rtx_insn *insn = NEXT_INSN (current_sched_info->prev_head); insn != current_sched_info->next_tail; insn = NEXT_INSN (insn)) gcc_assert (!SCHED_GROUP_P (insn)); -#endif + } last_scheduled_insn = NULL; init_insn_group_barriers (); @@ -9299,7 +9297,7 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) } } -#ifdef ENABLE_CHECKING + if (flag_checking) { /* Assert right calculation of middle_bundle_stops. */ int num = best_state->middle_bundle_stops; @@ -9332,8 +9330,7 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) end_bundle = next_insn == NULL_RTX || next_insn == tail || (INSN_P (next_insn) - && recog_memoized (next_insn) - == CODE_FOR_bundle_selector); + && recog_memoized (next_insn) == CODE_FOR_bundle_selector); if (recog_memoized (insn) == CODE_FOR_insn_group_barrier && !start_bundle && !end_bundle && next_insn @@ -9346,7 +9343,6 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) gcc_assert (num == 0); } -#endif free (index_to_bundle_states); finish_bundle_state_table (); diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index bfc19f3..37b1af2 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -6118,9 +6118,9 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int n_insns ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING /* Check that all instructions have DFA reservations and that all instructions can be issued from a clean state. */ + if (flag_checking) { rtx_insn *insn; state_t state; @@ -6139,7 +6139,6 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, } } } -#endif /* Setup target cpu. */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index bbdd142..53b86af 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -12906,15 +12906,13 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */ op[nopnds++] = GEN_INT (1); -#ifdef ENABLE_CHECKING + if (flag_checking) attr |= RS6000_BTC_UNARY; -#endif break; case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */ op[nopnds++] = GEN_INT (0); -#ifdef ENABLE_CHECKING + if (flag_checking) attr |= RS6000_BTC_UNARY; -#endif break; default: break; @@ -12935,7 +12933,8 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) op[nopnds++] = cr; } -#ifdef ENABLE_CHECKING + if (flag_checking) + { int expected_nopnds = 0; if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY) expected_nopnds = 1; @@ -12948,8 +12947,9 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) if (uses_spr) expected_nopnds += 2; - gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS); -#endif + gcc_assert (nopnds == expected_nopnds + && nopnds <= MAX_HTM_OPERANDS); + } switch (nopnds) { @@ -24325,7 +24325,7 @@ rs6000_emit_prologue (void) prior to it, when r12 is not used here for other purposes. */ rtx_insn *sp_adjust = 0; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Track and check usage of r0, r11, r12. */ int reg_inuse = using_static_chain_p ? 1 << 11 : 0; #define START_USE(R) do \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index cad1551..02da097 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1479,15 +1479,10 @@ enum reg_class extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; -#if ENABLE_CHECKING #define REGNO_REG_CLASS(REGNO) \ - (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ + (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ rs6000_regno_regclass[(REGNO)]) -#else -#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] -#endif - /* Register classes for various constraints that are based on the target switches. */ enum r6000_reg_class_enum { diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 5e7b944..d1b580e 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -1338,7 +1338,7 @@ visium_setup_incoming_varargs (cumulative_args_t pcum_v, local_args_so_far.p = &local_copy; locargs = get_cumulative_args (pcum_v); -#ifdef ENABLE_CHECKING +#if CHECKING_P local_args_so_far.magic = CUMULATIVE_ARGS_MAGIC; #endif diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9250b6..934711b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2015-10-29 Mikhail Maltsev + + * config/alpha/alpha.c (alpha_function_arg): Use gcc_checking_assert, + flag_checking and/or CHECKING_P to eliminate conditional compilation + on ENABLE_CHECKING. + * config/arm/arm.c (arm_unwind_emit_sequence): Likewise. + * config/bfin/bfin.c (hwloop_optimize): Likewise. + * config/i386/i386.c (ix86_print_operand_address): Likewise. + (output_387_binary_op): Likewise. + * config/ia64/ia64.c (ia64_sched_init, bundling): Likewise. + * config/m68k/m68k.c (m68k_sched_md_init_global): Likewise. + * config/rs6000/rs6000.c (htm_expand_builtin, rs6000_emit_prologue): + Likewise. + * config/rs6000/rs6000.h: Likewise. + * config/visium/visium.c (visium_setup_incoming_varargs): Likewise. + 2015-10-29 Kaz Kojima * config/sh/sh.opt (mfdpic): Add missing period. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index d22bf67..11da372 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -5558,11 +5558,9 @@ alpha_function_arg (cumulative_args_t cum_v, machine_mode mode, basereg = 16; else { -#ifdef ENABLE_CHECKING /* With alpha_split_complex_arg, we shouldn't see any raw complex values here. */ - gcc_assert (!COMPLEX_MODE_P (mode)); -#endif + gcc_checking_assert (!COMPLEX_MODE_P (mode)); /* Set up defaults for FP operands passed in FP registers, and integral operands passed in integer registers. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a598c84..7c72a81 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -26857,20 +26857,21 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) else asm_fprintf (asm_out_file, "%r", reg); -#ifdef ENABLE_CHECKING - /* Check that the addresses are consecutive. */ - e = XEXP (SET_DEST (e), 0); - if (GET_CODE (e) == PLUS) - gcc_assert (REG_P (XEXP (e, 0)) - && REGNO (XEXP (e, 0)) == SP_REGNUM - && CONST_INT_P (XEXP (e, 1)) - && offset == INTVAL (XEXP (e, 1))); - else - gcc_assert (i == 1 - && REG_P (e) - && REGNO (e) == SP_REGNUM); - offset += reg_size; -#endif + if (flag_checking) + { + /* Check that the addresses are consecutive. */ + e = XEXP (SET_DEST (e), 0); + if (GET_CODE (e) == PLUS) + gcc_assert (REG_P (XEXP (e, 0)) + && REGNO (XEXP (e, 0)) == SP_REGNUM + && CONST_INT_P (XEXP (e, 1)) + && offset == INTVAL (XEXP (e, 1))); + else + gcc_assert (i == 1 + && REG_P (e) + && REGNO (e) == SP_REGNUM); + offset += reg_size; + } } fprintf (asm_out_file, "}\n"); if (padfirst) diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 7334a52..6a5f90a 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -3792,8 +3792,7 @@ hwloop_optimize (hwloop_info loop) edge e; edge_iterator ei; -#ifdef ENABLE_CHECKING - if (loop->head != loop->incoming_dest) + if (flag_checking && loop->head != loop->incoming_dest) { /* We aren't entering the loop at the top. Since we've established that the loop is entered only at one point, this means there @@ -3803,7 +3802,6 @@ hwloop_optimize (hwloop_info loop) FOR_EACH_EDGE (e, ei, loop->head->preds) gcc_assert (!(e->flags & EDGE_FALLTHRU)); } -#endif emit_insn_before (seq, BB_HEAD (loop->head)); seq = emit_label_before (gen_label_rtx (), seq); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8476677..913dc00 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -17348,22 +17348,23 @@ ix86_print_operand_address (FILE *file, rtx addr) /* Print SImode register names to force addr32 prefix. */ if (SImode_address_operand (addr, VOIDmode)) { -#ifdef ENABLE_CHECKING - gcc_assert (TARGET_64BIT); - switch (GET_CODE (addr)) + if (flag_checking) { - case SUBREG: - gcc_assert (GET_MODE (addr) == SImode); - gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); - break; - case ZERO_EXTEND: - case AND: - gcc_assert (GET_MODE (addr) == DImode); - break; - default: - gcc_unreachable (); + gcc_assert (TARGET_64BIT); + switch (GET_CODE (addr)) + { + case SUBREG: + gcc_assert (GET_MODE (addr) == SImode); + gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); + break; + case ZERO_EXTEND: + case AND: + gcc_assert (GET_MODE (addr) == DImode); + break; + default: + gcc_unreachable (); + } } -#endif gcc_assert (!code); code = 'k'; } @@ -17620,10 +17621,10 @@ output_387_binary_op (rtx insn, rtx *operands) const char *ssep; int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]); -#ifdef ENABLE_CHECKING /* Even if we do not want to check the inputs, this documents input constraints. Which helps in understanding the following code. */ - if (STACK_REG_P (operands[0]) + if (flag_checking + && STACK_REG_P (operands[0]) && ((REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]) && (STACK_REG_P (operands[2]) || MEM_P (operands[2]))) @@ -17633,8 +17634,7 @@ output_387_binary_op (rtx insn, rtx *operands) && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2]))) ; /* ok */ else - gcc_assert (is_sse); -#endif + gcc_checking_assert (is_sse); switch (GET_CODE (operands[3])) { diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 8791138..d92af17 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6125,7 +6125,7 @@ struct reg_write_state /* Cumulative info for the current instruction group. */ struct reg_write_state rws_sum[NUM_REGS]; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Bitmap whether a register has been written in the current insn. */ HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) / HOST_BITS_PER_WIDEST_FAST_INT]; @@ -7293,15 +7293,13 @@ ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int max_ready ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING - rtx_insn *insn; - - if (!sel_sched_p () && reload_completed) - for (insn = NEXT_INSN (current_sched_info->prev_head); - insn != current_sched_info->next_tail; - insn = NEXT_INSN (insn)) - gcc_assert (!SCHED_GROUP_P (insn)); -#endif + if (flag_checking && !sel_sched_p () && reload_completed) + { + for (rtx_insn *insn = NEXT_INSN (current_sched_info->prev_head); + insn != current_sched_info->next_tail; + insn = NEXT_INSN (insn)) + gcc_assert (!SCHED_GROUP_P (insn)); + } last_scheduled_insn = NULL; init_insn_group_barriers (); @@ -9299,54 +9297,52 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) } } -#ifdef ENABLE_CHECKING - { - /* Assert right calculation of middle_bundle_stops. */ - int num = best_state->middle_bundle_stops; - bool start_bundle = true, end_bundle = false; - - for (insn = NEXT_INSN (prev_head_insn); - insn && insn != tail; - insn = NEXT_INSN (insn)) - { - if (!INSN_P (insn)) - continue; - if (recog_memoized (insn) == CODE_FOR_bundle_selector) - start_bundle = true; - else - { - rtx_insn *next_insn; - - for (next_insn = NEXT_INSN (insn); - next_insn && next_insn != tail; - next_insn = NEXT_INSN (next_insn)) - if (INSN_P (next_insn) - && (ia64_safe_itanium_class (next_insn) - != ITANIUM_CLASS_IGNORE - || recog_memoized (next_insn) - == CODE_FOR_bundle_selector) - && GET_CODE (PATTERN (next_insn)) != USE - && GET_CODE (PATTERN (next_insn)) != CLOBBER) - break; + if (flag_checking) + { + /* Assert right calculation of middle_bundle_stops. */ + int num = best_state->middle_bundle_stops; + bool start_bundle = true, end_bundle = false; - end_bundle = next_insn == NULL_RTX - || next_insn == tail - || (INSN_P (next_insn) - && recog_memoized (next_insn) - == CODE_FOR_bundle_selector); - if (recog_memoized (insn) == CODE_FOR_insn_group_barrier - && !start_bundle && !end_bundle - && next_insn - && !unknown_for_bundling_p (next_insn)) - num--; - - start_bundle = false; - } - } + for (insn = NEXT_INSN (prev_head_insn); + insn && insn != tail; + insn = NEXT_INSN (insn)) + { + if (!INSN_P (insn)) + continue; + if (recog_memoized (insn) == CODE_FOR_bundle_selector) + start_bundle = true; + else + { + rtx_insn *next_insn; + + for (next_insn = NEXT_INSN (insn); + next_insn && next_insn != tail; + next_insn = NEXT_INSN (next_insn)) + if (INSN_P (next_insn) + && (ia64_safe_itanium_class (next_insn) + != ITANIUM_CLASS_IGNORE + || recog_memoized (next_insn) + == CODE_FOR_bundle_selector) + && GET_CODE (PATTERN (next_insn)) != USE + && GET_CODE (PATTERN (next_insn)) != CLOBBER) + break; + + end_bundle = next_insn == NULL_RTX + || next_insn == tail + || (INSN_P (next_insn) + && recog_memoized (next_insn) == CODE_FOR_bundle_selector); + if (recog_memoized (insn) == CODE_FOR_insn_group_barrier + && !start_bundle && !end_bundle + && next_insn + && !unknown_for_bundling_p (next_insn)) + num--; + + start_bundle = false; + } + } - gcc_assert (num == 0); - } -#endif + gcc_assert (num == 0); + } free (index_to_bundle_states); finish_bundle_state_table (); diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index bfc19f3..37b1af2 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -6118,28 +6118,27 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int n_insns ATTRIBUTE_UNUSED) { -#ifdef ENABLE_CHECKING /* Check that all instructions have DFA reservations and that all instructions can be issued from a clean state. */ - { - rtx_insn *insn; - state_t state; + if (flag_checking) + { + rtx_insn *insn; + state_t state; - state = alloca (state_size ()); + state = alloca (state_size ()); - for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) - { - if (INSN_P (insn) && recog_memoized (insn) >= 0) - { - gcc_assert (insn_has_dfa_reservation_p (insn)); + for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) + { + if (INSN_P (insn) && recog_memoized (insn) >= 0) + { + gcc_assert (insn_has_dfa_reservation_p (insn)); - state_reset (state); - if (state_transition (state, insn) >= 0) - gcc_unreachable (); - } - } - } -#endif + state_reset (state); + if (state_transition (state, insn) >= 0) + gcc_unreachable (); + } + } + } /* Setup target cpu. */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index bbdd142..53b86af 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -12906,15 +12906,13 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */ case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */ op[nopnds++] = GEN_INT (1); -#ifdef ENABLE_CHECKING - attr |= RS6000_BTC_UNARY; -#endif + if (flag_checking) + attr |= RS6000_BTC_UNARY; break; case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */ op[nopnds++] = GEN_INT (0); -#ifdef ENABLE_CHECKING - attr |= RS6000_BTC_UNARY; -#endif + if (flag_checking) + attr |= RS6000_BTC_UNARY; break; default: break; @@ -12935,21 +12933,23 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp) op[nopnds++] = cr; } -#ifdef ENABLE_CHECKING - int expected_nopnds = 0; - if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY) - expected_nopnds = 1; - else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY) - expected_nopnds = 2; - else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY) - expected_nopnds = 3; - if (!(attr & RS6000_BTC_VOID)) - expected_nopnds += 1; - if (uses_spr) - expected_nopnds += 2; + if (flag_checking) + { + int expected_nopnds = 0; + if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY) + expected_nopnds = 1; + else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY) + expected_nopnds = 2; + else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY) + expected_nopnds = 3; + if (!(attr & RS6000_BTC_VOID)) + expected_nopnds += 1; + if (uses_spr) + expected_nopnds += 2; - gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS); -#endif + gcc_assert (nopnds == expected_nopnds + && nopnds <= MAX_HTM_OPERANDS); + } switch (nopnds) { @@ -24325,7 +24325,7 @@ rs6000_emit_prologue (void) prior to it, when r12 is not used here for other purposes. */ rtx_insn *sp_adjust = 0; -#ifdef ENABLE_CHECKING +#if CHECKING_P /* Track and check usage of r0, r11, r12. */ int reg_inuse = using_static_chain_p ? 1 << 11 : 0; #define START_USE(R) do \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index cad1551..02da097 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1479,15 +1479,10 @@ enum reg_class extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; -#if ENABLE_CHECKING #define REGNO_REG_CLASS(REGNO) \ - (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ + (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ rs6000_regno_regclass[(REGNO)]) -#else -#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] -#endif - /* Register classes for various constraints that are based on the target switches. */ enum r6000_reg_class_enum { diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 5e7b944..d1b580e 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -1338,7 +1338,7 @@ visium_setup_incoming_varargs (cumulative_args_t pcum_v, local_args_so_far.p = &local_copy; locargs = get_cumulative_args (pcum_v); -#ifdef ENABLE_CHECKING +#if CHECKING_P local_args_so_far.magic = CUMULATIVE_ARGS_MAGIC; #endif