From patchwork Wed Sep 23 08:49:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 521631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 703FD14012C for ; Wed, 23 Sep 2015 18:50:14 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=kAt7MBlw; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=CtrsttbSo97F9JAcuCmFugXaQ/WwYmMu+SYNPuthb6e6AErGpq2JN 4f/27uDldFlCT84tXXLVNu2oMnho9qou64gLrnPBFNHP02hnPCk3cAbspW9jupw6 1SmYTo3QPcHBPSiGo9NP/MTQ/zKeETT1+Jpq55DXLPR4yheqMV9GWI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; s=default; bh=NQLJWZDL+N35lIQ2qzsx/+ca56o=; b=kAt7MBlw6urEfpvoYN3aiav90lj0 ip+WZeqzYEj8HYbzRaCjVxSuoHHDhSVA9Mya68Rk+gQL/3E78vhoamBMj1s5CTf0 I8TwsSZ7Kw3sQieKFemanjIZ+qOPMKbX3xDRie+5/ysdbu/kdKXwf7jIeQC+IKQ6 8s/Qppu15q0Ruto= Received: (qmail 94436 invoked by alias); 23 Sep 2015 08:50:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90734 invoked by uid 89); 23 Sep 2015 08:50:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Sep 2015 08:50:01 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-10-umF8fSSEQ-C0VFK-TGZtrg-1; Wed, 23 Sep 2015 09:49:56 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 23 Sep 2015 09:49:56 +0100 Message-ID: <560267B4.5070809@arm.com> Date: Wed, 23 Sep 2015 09:49:56 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Michael Collison , GCC Patches , Ramana Radhakrishnan Subject: Re: [ARM] Use vector wide add for mixed-mode adds References: <5601E9B9.5060600@linaro.org> In-Reply-To: <5601E9B9.5060600@linaro.org> X-MC-Unique: umF8fSSEQ-C0VFK-TGZtrg-1 X-IsSubscribed: yes Hi Michael, On 23/09/15 00:52, Michael Collison wrote: > This is a modified version of the previous patch that removes the > documentation and read-md.c fixes. These patches have been submitted > separately and approved. > > This patch is designed to address code that was not being vectorized due > to missing widening patterns in the ARM backend. Code such as: > > int t6(int len, void * dummy, short * __restrict x) > { > len = len & ~31; > int result = 0; > __asm volatile (""); > for (int i = 0; i < len; i++) > result += x[i]; > return result; > } > > Validated on arm-none-eabi, arm-none-linux-gnueabi, > arm-none-linux-gnueabihf, and armeb-none-linux-gnueabihf. > > 2015-09-22 Michael Collison > > * config/arm/neon.md (widen_sum): New patterns > where mode is VQI to improve mixed mode add vectorization. > Please list all the new define_expands and define_insns in the changelog. Also, please add an ChangeLog entry for the testsuite additions. The approach looks ok to me with a few comments on some parts of the patch itself. +(define_insn "vec_sel_widen_ssum_hi3" + [(set (match_operand: 0 "s_register_operand" "=w") + (plus: (sign_extend: (vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w") + (match_operand:VQI 2 "vect_par_constant_high" ""))) + (match_operand: 3 "s_register_operand" "0")))] + "TARGET_NEON" + "vaddw.\t%q0, %q3, %f1" + [(set_attr "type" "neon_add_widen") + (set_attr "length" "8")] +) This is a single instruction, and it has a length of 4, so no need to override the length attribute. Same with the other define_insns in this patch. +/* { dg-final { scan-assembler "vaddw\.s16" } } */ + + + Stray trailing newlines. Similar comments for the other testcases. Thanks, Kyrill diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddws16.c b/gcc/testsuite/gcc.target/arm/neon-vaddws16.c new file mode 100644 index 0000000..ed10669 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddws16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_hw } */ The arm_neon_hw check is usually used when you want to run the tests. Since this is a compile-only tests you just need arm_neon_ok. +/* { dg-add-options arm_neon_ok } */ +/* { dg-options "-O3" } */ + + +int +t6(int len, void * dummy, short * __restrict x) +{ + len = len & ~31; + int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} +