From patchwork Thu Jul 16 15:20:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 496729 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9BAF11402A9 for ; Fri, 17 Jul 2015 01:21:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=u0el1B81; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=nEHXTF9vaTaCLHg4F28QYgvpNsscGXnSEMUNQu7q0mO mjC8tqxuM8p9Fy/zNqWAoZ89NA2havz+ZTpXELwChx4EEo1gMuC0yFPkscor/kT6 t/mSmjuqAxflpD5NPMjk+dfuLiKS3bFjoJ4mkfsuns8HcHiGn+FVWLr1VLkxZ1Wk = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=PMaiISIu8UFtKc+LaXg9XxMlbQk=; b=u0el1B8140FIZcNpz ml/iigz2KI+EV9a+b33oWrduTqoMFt9YrzWCD5FrInez38m63PJ2vgDnb+LaImQA RVc55N+snHRp9/Lzcr7A+ZytS2prRDVLwTpQu3dGkd7Tnq7fUcF6Vgg+BmSJFD+B WguAHCmURt4L5oRiNnto4xRAoM= Received: (qmail 42603 invoked by alias); 16 Jul 2015 15:20:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 42358 invoked by uid 89); 16 Jul 2015 15:20:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 16 Jul 2015 15:20:49 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-34-l5wJfioOT3GHBIoGlxcKjQ-1; Thu, 16 Jul 2015 16:20:42 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 16 Jul 2015 16:20:42 +0100 Message-ID: <55A7CBCA.3040504@arm.com> Date: Thu, 16 Jul 2015 16:20:42 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64][4/14] Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769 X-MC-Unique: l5wJfioOT3GHBIoGlxcKjQ-1 X-IsSubscribed: yes Hi all, This patch transforms the Cortex-A53 erratum 835769 workaround checks into a macro. This way we don't have to override aarch64_fix_a53_err835769 in the default case and this allows us to keep track of when the user doesn't specify this option, which may come in handy later on when we decide the inlining rules. This patch also makes TARGET_FIX_ERR_A53_835769_DEFAULT unconditionally defined to 0 or 1, so that we don't have to check it if #ifdefs. Bootstrapped and tested as part of series on aarch64. Checked that the workaround is applied as previously. Ok for trunk? 2015-07-16 Kyrylo Tkachov * config/aarch64/aarch64.h (TARGET_FIX_ERR_A53_835769_DEFAULT): Always define to 0 or 1. (TARGET_FIX_ERR_A53_835769): New macro. * config/aarch64/aarch64.c (aarch64_override_options_internal): Remove handling of opts->x_aarch64_fix_a53_err835769. (aarch64_madd_needs_nop): Check for TARGET_FIX_ERR_A53_835769 rather than aarch64_fix_a53_err835769. * config/aarch64/aarch64-elf-raw.h: Update for above changes. * config/aarch64/aarch64-linux.h: Likewise. commit 12e50e9fdcb86b0a4c73b3b43d92c386e9504637 Author: Kyrylo Tkachov Date: Thu May 21 09:49:12 2015 +0100 [AArch64][4/N] Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769 diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h index bd5e51c..66b4c8b 100644 --- a/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc/config/aarch64/aarch64-elf-raw.h @@ -27,7 +27,7 @@ " crtend%O%s crtn%O%s " \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" -#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT +#if TARGET_FIX_ERR_A53_835769_DEFAULT #define CA53_ERR_835769_SPEC \ " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}" #else diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h index 1600a32..b9d7805 100644 --- a/gcc/config/aarch64/aarch64-linux.h +++ b/gcc/config/aarch64/aarch64-linux.h @@ -52,7 +52,7 @@ " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" #endif -#ifdef TARGET_FIX_ERR_A53_843419_DEFAULT +#if TARGET_FIX_ERR_A53_843419_DEFAULT #define CA53_ERR_843419_SPEC \ " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}" #else diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5ea65e3..aff23d6 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7552,15 +7552,6 @@ aarch64_override_options_internal (struct gcc_options *opts) if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2)) opts->x_flag_strict_volatile_bitfields = 1; - if (opts->x_aarch64_fix_a53_err835769 == 2) - { -#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT - opts->x_aarch64_fix_a53_err835769 = 1; -#else - opts->x_aarch64_fix_a53_err835769 = 0; -#endif - } - /* -mgeneral-regs-only sets a mask in target_flags, make sure that aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags in case some code tries reading aarch64_isa_flags directly to check if @@ -9004,7 +8995,7 @@ aarch64_madd_needs_nop (rtx_insn* insn) rtx_insn *prev; rtx body; - if (!aarch64_fix_a53_err835769) + if (!TARGET_FIX_ERR_A53_835769) return false; if (recog_memoized (insn) < 0) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2a097af..d2d1ebf 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -233,6 +233,20 @@ extern unsigned long aarch64_isa_flags; /* CRC instructions that can be enabled through +crc arch extension. */ #define TARGET_CRC32 (AARCH64_ISA_CRC) +/* Make sure this is always defined so we don't have to check for ifdefs + but rather use normal ifs. */ +#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT +#define TARGET_FIX_ERR_A53_835769_DEFAULT 0 +#else +#undef TARGET_FIX_ERR_A53_835769_DEFAULT +#define TARGET_FIX_ERR_A53_835769_DEFAULT 1 +#endif + +/* Apply the workaround for Cortex-A53 erratum 835769. */ +#define TARGET_FIX_ERR_A53_835769 \ + ((aarch64_fix_a53_err835769 == 2) \ + ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: