From patchwork Tue Jul 7 12:36:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 492176 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 90EC51402C2 for ; Tue, 7 Jul 2015 22:37:27 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=d0oyWQ4z; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; q=dns; s=default; b=OhlY02j44RzMUFP6h3+dRTtPJ+443 Tx9Ls/oruQyaWiJstNhygDhDflqfZRpsNnFlrqiVFv0pG8/mNPoAnxKzBXBAyqb6 YI0bDBtA3NGeTegGZQ/LNvXBVASbqiQxVlrdLfVOXKGHidkE4iSlD+6nbs1vEeZk ULUmb2DRVPibL4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; s=default; bh=RSeUKM9k4o7Ghr0cSedDBKxyWkY=; b=d0o yWQ4zo1PyGXE+uYIidkA6bDeulLzBerNcjcibCQeUM340h5zohkI3Y4A9kFmKOMK eJIKEGicgn1HR29NexRn2OlsSW0bDwo2EvUXFsg3NRxXn9sNp3lUfMU6z3f7nM69 nhQOcB8PSH9DC0ufbRwnhd0mv6zzoykUT4IzdnTA= Received: (qmail 109253 invoked by alias); 7 Jul 2015 12:36:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 109180 invoked by uid 89); 7 Jul 2015 12:36:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 07 Jul 2015 12:36:41 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-26-X-zTHKWhT7-SKs6YxVkvtQ-1 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 7 Jul 2015 13:36:34 +0100 Message-ID: <559BC7D2.9050506@arm.com> Date: Tue, 07 Jul 2015 13:36:34 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 11/16][AArch64] Implement vcvt_{,high_}f16_f32 In-Reply-To: <559BC6EC.3000907@arm.com> X-MC-Unique: X-zTHKWhT7-SKs6YxVkvtQ-1 X-IsSubscribed: yes This comes from https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01343.html but the other/unrelated intrinsics have moved into the next patch. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf): Reparameterize to... (aarch64_float_truncate_lo_): ...this, for both V2SF and V4HF. (aarch64_float_truncate_hi_v4sf): Reparameterize to... (aarch64_float_truncate_hi_): ...this, for both V4SF and V8HF. * config/aarch64/aarch64-simd-builtins.def (float_truncate_hi_): Add v8hf variant. (float_truncate_lo_): Use BUILTIN_VDF iterator. * config/aarch64/arm_neon.h (vcvt_f16_f32, vcvt_high_f16_f32): New. * config/aarch64/iterators.md (VDF, Vdtype): New. (VWIDE, Vmwtype): Add cases for V4HF and V2SF. commit 5007fafedc8469ab645edfe65fbf41f75fc74750 Author: Alan Lawrence Date: Tue Dec 2 18:30:05 2014 +0000 AArch64 4/N v2: float_truncate_lo/hi diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 4dd2bc7..8bcab72 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -363,9 +363,10 @@ VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) VAR1 (BINOP, float_truncate_hi_, 0, v4sf) + VAR1 (BINOP, float_truncate_hi_, 0, v8hf) VAR1 (UNOP, float_extend_lo_, 0, v2df) - VAR1 (UNOP, float_truncate_lo_, 0, v2sf) + BUILTIN_VDF (UNOP, float_truncate_lo_, 0) /* Implemented by aarch64_ld1. */ BUILTIN_VALL_F16 (LOAD1, ld1, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5cc45ed..2dc54e1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1726,23 +1726,23 @@ ;; Float narrowing operations. -(define_insn "aarch64_float_truncate_lo_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=w") - (float_truncate:V2SF - (match_operand:V2DF 1 "register_operand" "w")))] +(define_insn "aarch64_float_truncate_lo_" + [(set (match_operand:VDF 0 "register_operand" "=w") + (float_truncate:VDF + (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" - "fcvtn\\t%0.2s, %1.2d" + "fcvtn\\t%0., %1" [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) -(define_insn "aarch64_float_truncate_hi_v4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") - (vec_concat:V4SF - (match_operand:V2SF 1 "register_operand" "0") - (float_truncate:V2SF - (match_operand:V2DF 2 "register_operand" "w"))))] +(define_insn "aarch64_float_truncate_hi_" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand:VDF 1 "register_operand" "0") + (float_truncate:VDF + (match_operand: 2 "register_operand" "w"))))] "TARGET_SIMD" - "fcvtn2\\t%0.4s, %2.2d" + "fcvtn2\\t%0., %2" [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index d61e619..b915754 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5726,12 +5726,8 @@ vaddlvq_u32 (uint32x4_t a) result; \ }) -/* vcvt_f16_f32 not supported */ - /* vcvt_f32_f16 not supported */ -/* vcvt_high_f16_f32 not supported */ - /* vcvt_high_f32_f16 not supported */ #define vcvt_n_f32_s32(a, b) \ @@ -13098,6 +13094,18 @@ vcntq_u8 (uint8x16_t __a) /* vcvt (double -> float). */ +__extension__ static __inline float16x4_t __attribute__ ((__always_inline__)) +vcvt_f16_f32 (float32x4_t __a) +{ + return __builtin_aarch64_float_truncate_lo_v4hf (__a); +} + +__extension__ static __inline float16x8_t __attribute__ ((__always_inline__)) +vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b) +{ + return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b); +} + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vcvt_f32_f64 (float64x2_t __a) { diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 96920cf..f6094b1 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -41,6 +41,9 @@ ;; Iterator for General Purpose Float regs, inc float16_t. (define_mode_iterator GPF_F16 [HF SF DF]) +;; Double vector modes. +(define_mode_iterator VDF [V2SF V4HF]) + ;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) @@ -452,6 +455,9 @@ (SI "V2SI") (DI "V2DI") (DF "V2DF")]) +;; Register suffix for double-length mode. +(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) + ;; Double modes of vector modes (lower case). (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") (V4HF "v8hf") @@ -485,7 +491,8 @@ (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI") (V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") - (HI "SI") (SI "DI")] + (HI "SI") (SI "DI") + (V4HF "V4SF") (V2SF "V2DF")] ) @@ -498,6 +505,7 @@ (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") (V2SI ".2d") (V16QI ".8h") (V8HI ".4s") (V4SI ".2d") + (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) ;; Lower part register suffixes for VQW.