From patchwork Tue Jul 7 12:35:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 492172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 04EB21402B8 for ; Tue, 7 Jul 2015 22:36:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=HfoXRFFP; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; q=dns; s=default; b=YSmhTJWRShSrZ8dQAj/lis2sJDlp1 Xkv+OxSXW+McBRoBoqufcvRRcrYWFlQHJsMewRRL2DaK+pOCNlMtY3QeD5r+qhwB u8xC6ET8IafbqBThYZbR56lLuMjui/FglSCLcQZHG3khoEDPeNMS2GIyFugdp6ox +CiDDkSgw6xAqM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; s=default; bh=nzJkSoh+s4Zd1OzsAM/x+JVIs0s=; b=Hfo XRFFPApF+h0Rhp6UTzHgruNu0kBzbNuDBM1tt94OR9ZmZwpLJ/4i0lSnDyKlK/8z dh+oyvR43tyqR1RoRkEGsmPmMNFXWyRUaM3kR6em4G8WHR54Oh1cjNGcYnO/l7ki o4/bBF3aClGM1nRZ3aVDdkbjwsi0eRXFKcOEirNU= Received: (qmail 99684 invoked by alias); 7 Jul 2015 12:35:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 99619 invoked by uid 89); 7 Jul 2015 12:35:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 07 Jul 2015 12:35:36 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-36-v0dyMU0ySwWmibDd07UVyw-1 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 7 Jul 2015 13:35:30 +0100 Message-ID: <559BC792.5050905@arm.com> Date: Tue, 07 Jul 2015 13:35:30 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 7/16][AArch64] Add basic fp16 support In-Reply-To: <559BC6EC.3000907@arm.com> X-MC-Unique: v0dyMU0ySwWmibDd07UVyw-1 X-IsSubscribed: yes Same as https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01340.html except that two of the tests have been moved into the next patch. (The remaining test is AArch64 only.) gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New. (aarch64_init_builtins): Make aarch64_fp16_type_node, use for __fp16. * config/aarch64/aarch64-modes.def: Add HFmode. * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FP16_FORMAT_IEEE and __ARM_FP16_ARGS. Set bit 1 of __ARM_FP. * config/aarch64/aarch64.c (aarch64_init_libfuncs, aarch64_promoted_type): New. (aarch64_float_const_representable_p): Disable HFmode. (aarch64_mangle_type): Mangle half-precision floats to "Dh". (TARGET_PROMOTED_TYPE): Define to aarch64_promoted_type. (TARGET_INIT_LIBFUNCS): Define to aarch64_init_libfuncs. * config/aarch64/aarch64.md (mov): Include HFmode using GPF_F16. (movhf_aarch64, extendhfsf2, extendhfdf2, truncsfhf2, truncdfhf2): New. * config/aarch64/iterators.md (GPF_F16): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/f16_movs_1.c: New test. commit 989af1492bbf268be1ecfae06f3303b90ae514c8 Author: Alan Lawrence Date: Tue Dec 2 12:57:39 2014 +0000 AArch64 1/6: Basic HFmode support (less tests), aarch64_fp16_type_node, patterns, mangling, predefines. No --fp16-format option. Disable constants as NYI. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index ec60955..cfb2dc1 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -439,6 +439,9 @@ static struct aarch64_simd_type_info aarch64_simd_types [] = { }; #undef ENTRY +/* This type is not SIMD-specific; it is the user-visible __fp16. */ +static tree aarch64_fp16_type_node = NULL_TREE; + static tree aarch64_simd_intOI_type_node = NULL_TREE; static tree aarch64_simd_intEI_type_node = NULL_TREE; static tree aarch64_simd_intCI_type_node = NULL_TREE; @@ -849,6 +852,12 @@ aarch64_init_builtins (void) = add_builtin_function ("__builtin_aarch64_set_fpsr", ftype_set_fpr, AARCH64_BUILTIN_SET_FPSR, BUILT_IN_MD, NULL, NULL_TREE); + aarch64_fp16_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (aarch64_fp16_type_node) = 16; + layout_type (aarch64_fp16_type_node); + + (*lang_hooks.types.register_builtin_type) (aarch64_fp16_type_node, "__fp16"); + if (TARGET_SIMD) aarch64_init_simd_builtins (); if (TARGET_CRC32) diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index b17b90d..c30059b 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -36,6 +36,10 @@ CC_MODE (CC_DLTU); CC_MODE (CC_DGEU); CC_MODE (CC_DGTU); +/* Half-precision floating point for arm_neon.h float16_t. */ +FLOAT_MODE (HF, 2, 0); +ADJUST_FLOAT_FORMAT (HF, &ieee_half_format); + /* Vector modes. */ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 17bae08..f338033 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8339,6 +8339,10 @@ aarch64_mangle_type (const_tree type) if (lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) return "St9__va_list"; + /* Half-precision float. */ + if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16) + return "Dh"; + /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for builtin types. */ if (TYPE_NAME (type) != NULL) @@ -9578,6 +9582,33 @@ aarch64_start_file (void) default_file_start(); } +static void +aarch64_init_libfuncs (void) +{ + /* Half-precision float operations. The compiler handles all operations + with NULL libfuncs by converting to SFmode. */ + + /* Conversions. */ + set_conv_libfunc (trunc_optab, HFmode, SFmode, "__gnu_f2h_ieee"); + set_conv_libfunc (sext_optab, SFmode, HFmode, "__gnu_h2f_ieee"); + + /* Arithmetic. */ + set_optab_libfunc (add_optab, HFmode, NULL); + set_optab_libfunc (sdiv_optab, HFmode, NULL); + set_optab_libfunc (smul_optab, HFmode, NULL); + set_optab_libfunc (neg_optab, HFmode, NULL); + set_optab_libfunc (sub_optab, HFmode, NULL); + + /* Comparisons. */ + set_optab_libfunc (eq_optab, HFmode, NULL); + set_optab_libfunc (ne_optab, HFmode, NULL); + set_optab_libfunc (lt_optab, HFmode, NULL); + set_optab_libfunc (le_optab, HFmode, NULL); + set_optab_libfunc (ge_optab, HFmode, NULL); + set_optab_libfunc (gt_optab, HFmode, NULL); + set_optab_libfunc (unord_optab, HFmode, NULL); +} + /* Target hook for c_mode_for_suffix. */ static machine_mode aarch64_c_mode_for_suffix (char suffix) @@ -9616,7 +9647,8 @@ aarch64_float_const_representable_p (rtx x) if (!CONST_DOUBLE_P (x)) return false; - if (GET_MODE (x) == VOIDmode) + /* We don't support HFmode constants yet. */ + if (GET_MODE (x) == VOIDmode || GET_MODE (x) == HFmode) return false; REAL_VALUE_FROM_CONST_DOUBLE (r, x); @@ -11551,6 +11583,14 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, return true; } +/* Implement TARGET_PROMOTED_TYPE to promote float16 to 32 bits. */ +static tree +aarch64_promoted_type (const_tree t) +{ + if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) + return float_type_node; + return NULL_TREE; +} #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST aarch64_address_cost @@ -11705,6 +11745,9 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, #undef TARGET_SCHED_REASSOCIATION_WIDTH #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width +#undef TARGET_PROMOTED_TYPE +#define TARGET_PROMOTED_TYPE aarch64_promoted_type + #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload @@ -11797,6 +11840,8 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ aarch64_vectorize_vec_perm_const_ok +#undef TARGET_INIT_LIBFUNCS +#define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs #undef TARGET_FIXED_CONDITION_CODE_REGS #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index a22c6e4..44fe4f9 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -57,7 +57,9 @@ if (TARGET_FLOAT) \ { \ builtin_define ("__ARM_FEATURE_FMA"); \ - builtin_define_with_int_value ("__ARM_FP", 0x0C); \ + builtin_define_with_int_value ("__ARM_FP", 0x0E); \ + builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ + builtin_define ("__ARM_FP16_ARGS"); \ } \ if (TARGET_SIMD) \ { \ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1efe57c..6eafa2c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -976,8 +976,8 @@ }) (define_expand "mov" - [(set (match_operand:GPF 0 "nonimmediate_operand" "") - (match_operand:GPF 1 "general_operand" ""))] + [(set (match_operand:GPF_F16 0 "nonimmediate_operand" "") + (match_operand:GPF_F16 1 "general_operand" ""))] "" " if (!TARGET_FLOAT) @@ -991,6 +991,26 @@ " ) +(define_insn "*movhf_aarch64" + [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] + "TARGET_FLOAT && (register_operand (operands[0], HFmode) + || register_operand (operands[1], HFmode))" + "@ + mov\\t%0.h[0], %w1 + umov\\t%w0, %1.h[0] + mov\\t%0.h[0], %1.h[0] + ldr\\t%h0, %1 + str\\t%h1, %0 + ldrh\\t%w0, %1 + strh\\t%w1, %0 + mov\\t%w0, %w1" + [(set_attr "type" "neon_from_gp,neon_to_gp,fmov,\ + f_loads,f_stores,load1,store1,mov_reg") + (set_attr "simd" "yes,yes,yes,*,*,*,*,*") + (set_attr "fp" "*,*,*,yes,yes,*,*,*")] +) + (define_insn "*movsf_aarch64" [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] @@ -4088,6 +4108,22 @@ [(set_attr "type" "f_cvt")] ) +(define_insn "extendhfsf2" + [(set (match_operand:SF 0 "register_operand" "=w") + (float_extend:SF (match_operand:HF 1 "register_operand" "w")))] + "TARGET_FLOAT" + "fcvt\\t%s0, %h1" + [(set_attr "type" "f_cvt")] +) + +(define_insn "extendhfdf2" + [(set (match_operand:DF 0 "register_operand" "=w") + (float_extend:DF (match_operand:HF 1 "register_operand" "w")))] + "TARGET_FLOAT" + "fcvt\\t%d0, %h1" + [(set_attr "type" "f_cvt")] +) + (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=w") (float_truncate:SF (match_operand:DF 1 "register_operand" "w")))] @@ -4096,6 +4132,22 @@ [(set_attr "type" "f_cvt")] ) +(define_insn "truncsfhf2" + [(set (match_operand:HF 0 "register_operand" "=w") + (float_truncate:HF (match_operand:SF 1 "register_operand" "w")))] + "TARGET_FLOAT" + "fcvt\\t%h0, %s1" + [(set_attr "type" "f_cvt")] +) + +(define_insn "truncdfhf2" + [(set (match_operand:HF 0 "register_operand" "=w") + (float_truncate:HF (match_operand:DF 1 "register_operand" "w")))] + "TARGET_FLOAT" + "fcvt\\t%h0, %d1" + [(set_attr "type" "f_cvt")] +) + (define_insn "fix_trunc2" [(set (match_operand:GPI 0 "register_operand" "=r") (fix:GPI (match_operand:GPF 1 "register_operand" "w")))] diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 498358a..a6b351b 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -38,6 +38,9 @@ ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) (define_mode_iterator GPF [SF DF]) +;; Iterator for General Purpose Float regs, inc float16_t. +(define_mode_iterator GPF_F16 [HF SF DF]) + ;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) diff --git a/gcc/testsuite/gcc.target/aarch64/f16_movs_1.c b/gcc/testsuite/gcc.target/aarch64/f16_movs_1.c new file mode 100644 index 0000000..6cb8086 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_movs_1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-fno-inline -O2" } */ + +#include + +__fp16 +func2 (__fp16 a, __fp16 b) +{ + return b; +} + +int +main (int argc, char **argv) +{ + __fp16 array[16]; + int i; + + for (i = 0; i < sizeof (array) / sizeof (array[0]); i++) + array[i] = i; + + array[0] = func2 (array[1], array[2]); + + __builtin_printf ("%f\n", array[0]); /* { dg-output "2.0" } */ + + return 0; +}