From patchwork Mon Jul 6 17:40:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 491724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0D46C1409F8 for ; Tue, 7 Jul 2015 03:40:30 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Ioo76lra; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=MFk11L/4vjkTHVmbIwxDVeQZ2nF2YfBeSvLp4mZo9jMwklD2QDeLh 9oeFBt0UG6w5ob6cRn1nJmaEosXEXg2b/jzeurvRaBeF1jNV30pAGwmCCwSBsJ30 YVU9ySyF2f1y4KbpBKQJfitboUCciEn3C5wRkFmIS2+LPBwTtoKv64= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; s=default; bh=/z4pPov1nNZjwFCtOT8JvB8O91c=; b=Ioo76lraw4I4LqjjfT68j2YtuKn1 TVvO7SzSlesF+eKla1Z5OFbZfvqQ8gX+tmYVV0XrLVLwrulnI2hf0jb05sMukXju MshH6InAFRcsCPLnXUdsMuDVQAc1/a6CZ1KzcWhjZW7dim2jQ6OZGO2+ae+Ij8aJ oNvtrEDD9X47JBg= Received: (qmail 47301 invoked by alias); 6 Jul 2015 17:40:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47208 invoked by uid 89); 6 Jul 2015 17:40:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 06 Jul 2015 17:40:11 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-36-PRIxtXsvQWiNJold0XozKg-1 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 6 Jul 2015 18:40:06 +0100 Message-ID: <559ABD76.2050508@arm.com> Date: Mon, 06 Jul 2015 18:40:06 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: Richard Earnshaw CC: "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH 2/2][ARM] fix movdi expander to avoid illegal ldrd/strd References: <5596A9C7.3040109@arm.com> <5596B56C.7070505@foss.arm.com> In-Reply-To: <5596B56C.7070505@foss.arm.com> X-MC-Unique: PRIxtXsvQWiNJold0XozKg-1 X-IsSubscribed: yes Richard Earnshaw wrote: > On 03/07/15 16:27, Alan Lawrence wrote: >> The previous patch caused a regression in >> gcc.c-torture/execute/20040709-1.c at -O0 (only), and the new >> align_rec2.c test fails, both outputting an illegal assembler >> instruction (ldrd on an odd-numbered reg) from output_move_double in >> arm.c. Most routes have checks against such an illegal instruction, but >> expanding a function call can directly name such impossible register >> (pairs), bypassing the normal checks. >> >> gcc/ChangeLog: >> >> * config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state. >> > > OK. Both patches, plus Jakub's test, pushed onto trunk (r221461/5/6), and gcc-5-branch (r225467/9/70), with an obvious comment fix to the movdi patch (LDRD's into, STRD's from), as below. Cheers, Alan Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 225457) +++ gcc/config/arm/arm.md (working copy) @@ -5481,6 +5481,42 @@ if (!REG_P (operands[0])) operands[1] = force_reg (DImode, operands[1]); } + if (REG_P (operands[0]) && REGNO (operands[0]) < FIRST_VIRTUAL_REGISTER + && !HARD_REGNO_MODE_OK (REGNO (operands[0]), DImode)) + { + /* Avoid LDRD's into an odd-numbered register pair in ARM state + when expanding function calls. */ + gcc_assert (can_create_pseudo_p ()); + if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1])) + { + /* Perform load into legal reg pair first, then move. */ + rtx reg = gen_reg_rtx (DImode); + emit_insn (gen_movdi (reg, operands[1])); + operands[1] = reg; + } + emit_move_insn (gen_lowpart (SImode, operands[0]), + gen_lowpart (SImode, operands[1])); + emit_move_insn (gen_highpart (SImode, operands[0]), + gen_highpart (SImode, operands[1])); + DONE; + } + else if (REG_P (operands[1]) && REGNO (operands[1]) < FIRST_VIRTUAL_REGISTER + && !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode)) + { + /* Avoid STRD's from an odd-numbered register pair in ARM state + when expanding function prologue. */ + gcc_assert (can_create_pseudo_p ()); + rtx split_dest = (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0])) + ? gen_reg_rtx (DImode) + : operands[0]; + emit_move_insn (gen_lowpart (SImode, split_dest), + gen_lowpart (SImode, operands[1])); + emit_move_insn (gen_highpart (SImode, split_dest), + gen_highpart (SImode, operands[1])); + if (split_dest != operands[0]) + emit_insn (gen_movdi (operands[0], split_dest)); + DONE; + } " )