From patchwork Tue Jun 23 16:03:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 487708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 454A01401AD for ; Wed, 24 Jun 2015 02:03:48 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=i1ZWlGku; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=ASPzBRG6shYW1/It2 VtBm1uL4ToGYOHYvvvYbAtOzsXa3EQ8Pr4mi7+NlG2zfe2PbaRpZBw6EyURJS/GB 1ZjPWlkT5H9FvDpl2WvelLPjmg0baYRC4r6vXHR82cjBYSt7lIQt1Myt4MId7wvd 4OeiSnjM9uklsFHWUYn0uz8pog= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=SSHT3WZpru5YgJotL3zmQtB LiII=; b=i1ZWlGku1iJcQLtZWoCODW15CKx5gceG8vtUo/Hh3VOMjumnxaQnSqa iotRN/zYR4wyKAW8ZqeVxuF6Ij99D0SgviQbkVH0yL1mxqN8lLyEqs2lGlaDMrma +aaNwUKqmw1ZtearSnWBM2BaeZGxtM8FdRPR6x8SCt/ObLpgm+l8= Received: (qmail 15745 invoked by alias); 23 Jun 2015 16:03:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15685 invoked by uid 89); 23 Jun 2015 16:03:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 23 Jun 2015 16:03:17 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-7-3Stc2WLvS96HqHjuc2uGZQ-1 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 23 Jun 2015 17:03:14 +0100 Message-ID: <55898341.4060701@arm.com> Date: Tue, 23 Jun 2015 17:03:13 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: James Greenhalgh CC: "gcc-patches@gcc.gnu.org" Subject: [PATCH 2/3][AArch64 nofp] Clarify docs for +nofp/-mgeneral-regs-only References: <557970C8.8060604@arm.com> <20150616103140.GA14076@arm.com> In-Reply-To: <20150616103140.GA14076@arm.com> X-MC-Unique: 3Stc2WLvS96HqHjuc2uGZQ-1 X-IsSubscribed: yes James Greenhalgh wrote: > >> -Generate code which uses only the general registers. >> +Generate code which uses only the general registers. Equivalent to feature > > The ARMARM uses "general-purpose registers" to refer to these registers, > we should match that style. > > s/Equivalent to feature/This is equivalent to the feature/ Done. >> -Feature modifiers used with @option{-march} and @option{-mcpu} can be one >> -the following: >> +Feature modifiers used with @option{-march} and @option{-mcpu} can be any of >> +the following, or their inverses @option{no@var{feature}}: > > s/inverses/inverse/ The grammar is quite difficult here, so have gone for "and their inverses" as the set of possibilities definitely includes 3 inverses. >> >> +As stated above, @option{crypto} implies @option{simd} implies @option{fp}. > > Drop the "As stated above". To my eye, beginning a sentence in lowercase looks very odd in pdf, and still a bit odd in html. Have changed to "That is"...? Tested with make pdf & make html. gcc/ChangeLog (unchanged): * doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd and (no)crypto. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d8e982c3aa338819df3785696c493a66c1f5b674..0579bf2ecf993bb56987e0bb9686925537ab61e3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12359,7 +12359,10 @@ Generate big-endian code. This is the default when GCC is configured for an @item -mgeneral-regs-only @opindex mgeneral-regs-only -Generate code which uses only the general registers. +Generate code which uses only the general-purpose registers. This is equivalent +to feature modifier @option{nofp} of @option{-march} or @option{-mcpu}, except +that @option{-mgeneral-regs-only} takes precedence over any conflicting feature +modifier regardless of sequence. @item -mlittle-endian @opindex mlittle-endian @@ -12498,20 +12501,22 @@ over the appropriate part of this option. @subsubsection @option{-march} and @option{-mcpu} Feature Modifiers @cindex @option{-march} feature modifiers @cindex @option{-mcpu} feature modifiers -Feature modifiers used with @option{-march} and @option{-mcpu} can be one -the following: +Feature modifiers used with @option{-march} and @option{-mcpu} can be any of +the following and their inverses @option{no@var{feature}}: @table @samp @item crc Enable CRC extension. @item crypto -Enable Crypto extension. This implies Advanced SIMD is enabled. +Enable Crypto extension. This also enables Advanced SIMD and floating-point +instructions. @item fp -Enable floating-point instructions. +Enable floating-point instructions. This is on by default for all possible +values for options @option{-march} and @option{-mcpu}. @item simd -Enable Advanced SIMD instructions. This implies floating-point instructions -are enabled. This is the default for all current possible values for options -@option{-march} and @option{-mcpu=}. +Enable Advanced SIMD instructions. This also enables floating-point +instructions. This is on by default for all possible values for options +@option{-march} and @option{-mcpu}. @item lse Enable Large System Extension instructions. @item pan @@ -12522,6 +12527,10 @@ Enable Limited Ordering Regions support. Enable ARMv8.1 Advanced SIMD instructions. @end table +That is, @option{crypto} implies @option{simd} implies @option{fp}. +Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only}) +implies @option{nosimd} implies @option{nocrypto}. + @node Adapteva Epiphany Options @subsection Adapteva Epiphany Options