From patchwork Thu Jun 11 11:29:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 483069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D6269140291 for ; Thu, 11 Jun 2015 21:30:06 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=BSkUWgRZ; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=PvwFUYFkLRY+a0M4jukt+nm+WTfBPuu593+CNiAgeNm fVAHOoa1UgPmBsbuo3M+orgpn4SjHecM+2IefzXlxI+lxagFUq8Uqmf6yKmO7FPt UYRidE21n4tS8pPHrDk5B2OW+bD9X7QBtbbu9zlA7aEMD3MrfGHH6q99J/Cwi7ZA = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=FT0W5krG/A+TBtTk4d0T0i1ACDg=; b=BSkUWgRZvrHj4mPFY YWYXROpJ03Nk9pYrN9ktsHOBEMaQZNXJXei4kNiYUl6F78cDRK3Cpeu14XtpkO4k cRe50+UkWKWBMKkiaXTRPmZ0YABS2Pe9ZbxR6YdUzkEuDRNXl68RbwNBAi+lMa4s vBsyUIoPBVM8jwW/tK6xXW0GAE= Received: (qmail 56060 invoked by alias); 11 Jun 2015 11:29:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 56036 invoked by uid 89); 11 Jun 2015 11:29:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 11 Jun 2015 11:29:56 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-22.uk.mimecast.lan; Thu, 11 Jun 2015 12:29:53 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 11 Jun 2015 12:29:53 +0100 Message-ID: <55797131.30407@arm.com> Date: Thu, 11 Jun 2015 12:29:53 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: James Greenhalgh Subject: [PATCH *2][AArch64] Fix ICEs with +nofp/-mgeneral-regs-only and improve error messages; clarify docs. X-MC-Unique: wM_FRouKSkW7IHwmXrd_Tw-1 X-IsSubscribed: yes Hi, This is a follow-up to Jim Wilson's patch fixing ICE's with -march=armv8-a+nofp, and the discussion here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00177.html The first patch improves the error messages to describe what kind of code caused the problem, and to error rather than "sorry" (we should not be sorry, the user has asked the compiler to do something that makes no sense!). Moreover, to issue an error, rather than ICE, on some testcases (supplied!). The error messages in aarch64_setup_incoming_varargs and aarch64_expand_builtin_va_start are then never reached as error() has already been called, so change them to asserts. Compiling with -mgeneral-regs-only on functions taking vector arguments, and simple arithmetic using float/double, all raise the error; on functions using vectors only internally not via ABI, at least some are handled by the midend using scalar code. The second patch cleans up the documentation in line with the previous discussion. OK for trunk? Thanks, Alan gcc/ChangeLog: * config/aarch64/aarch64-protos.h (aarch64_err_no_fpadvsimd): New. * config/aarch64/aarch64.md (mov/GPF, movtf): Use aarch64_err_no_fpadvsimd. * config/aarch64/aarch64.c (aarch64_err_no_fpadvsimd): New. (aarch64_layout_arg, aarch64_init_cumulative_args): Use aarch64_err_no_fpadvsimd if !TARGET_FLOAT and we need FP regs. (aarch64_expand_builtin_va_start, aarch64_setup_incoming_varargs): Turn error into assert, test TARGET_FLOAT. (aarch64_gimplify_va_arg_expr): Use aarch64_err_no_fpadvsimd, test TARGET_FLOAT. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mgeneral-regs_1.c: New file. * gcc.target/aarch64/mgeneral-regs_2.c: New file. * gcc.target/aarch64/nofp_1.c: New file. gcc/ChangeLog: * doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd and (no)crypto. commit 298595e5254183de5b4c1cd2acaed43949b4dd30 Author: Alan Lawrence Date: Mon Jan 19 12:18:02 2015 +0000 doc/invoke.texi, as approved, with whitespace. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e25bd62..0d62edf 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12359,7 +12359,10 @@ Generate big-endian code. This is the default when GCC is configured for an @item -mgeneral-regs-only @opindex mgeneral-regs-only -Generate code which uses only the general registers. +Generate code which uses only the general registers. Equivalent to feature +modifier @option{nofp} of @option{-march} or @option{-mcpu}, except that +@option{-mgeneral-regs-only} takes precedence over any conflicting feature +modifier regardless of sequence. @item -mlittle-endian @opindex mlittle-endian @@ -12498,22 +12501,28 @@ over the appropriate part of this option. @subsubsection @option{-march} and @option{-mcpu} Feature Modifiers @cindex @option{-march} feature modifiers @cindex @option{-mcpu} feature modifiers -Feature modifiers used with @option{-march} and @option{-mcpu} can be one -the following: +Feature modifiers used with @option{-march} and @option{-mcpu} can be any of +the following, or their inverses @option{no@var{feature}}: @table @samp @item crc Enable CRC extension. @item crypto -Enable Crypto extension. This implies Advanced SIMD is enabled. +Enable Crypto extension. This also enables Advanced SIMD and floating-point +instructions. @item fp -Enable floating-point instructions. +Enable floating-point instructions. This is on by default for all possible +values for options @option{-march} and @option{-mcpu}. @item simd -Enable Advanced SIMD instructions. This implies floating-point instructions -are enabled. This is the default for all current possible values for options -@option{-march} and @option{-mcpu=}. +Enable Advanced SIMD instructions. This also enables floating-point +instructions. This is on by default for all possible values for options +@option{-march} and @option{-mcpu}. @end table +As stated above, @option{crypto} implies @option{simd} implies @option{fp}. +Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only}) +implies @option{nosimd} implies @option{nocrypto}. + @node Adapteva Epiphany Options @subsection Adapteva Epiphany Options