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[*2,AArch64] Fix ICEs with +nofp/-mgeneral-regs-only and improve error messages; clarify docs.

Message ID 55797131.30407@arm.com
State New
Headers show

Commit Message

Alan Lawrence June 11, 2015, 11:29 a.m. UTC 
Hi,

This is a follow-up to Jim Wilson's patch fixing ICE's with -march=armv8-a+nofp,
and the discussion here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00177.html

The first patch improves the error messages to describe what kind of code caused
the problem, and to error rather than "sorry" (we should not be sorry, the user
has asked the compiler to do something that makes no sense!). Moreover, to issue
an error, rather than ICE, on some testcases (supplied!).

The error messages in aarch64_setup_incoming_varargs and
aarch64_expand_builtin_va_start are then never reached as error() has already
been called, so change them to asserts.

Compiling with -mgeneral-regs-only on functions taking vector arguments, and
simple arithmetic using float/double, all raise the error; on functions using
vectors only internally not via ABI, at least some are handled by the midend
using scalar code.


The second patch cleans up the documentation in line with the previous discussion.

OK for trunk?

Thanks, Alan


gcc/ChangeLog:

	* config/aarch64/aarch64-protos.h (aarch64_err_no_fpadvsimd): New.

	* config/aarch64/aarch64.md (mov<mode>/GPF, movtf): Use
	aarch64_err_no_fpadvsimd.

	* config/aarch64/aarch64.c (aarch64_err_no_fpadvsimd): New.
	(aarch64_layout_arg, aarch64_init_cumulative_args): Use
	aarch64_err_no_fpadvsimd if !TARGET_FLOAT and we need FP regs.
	(aarch64_expand_builtin_va_start, aarch64_setup_incoming_varargs):
	Turn error into assert, test TARGET_FLOAT.
	(aarch64_gimplify_va_arg_expr): Use aarch64_err_no_fpadvsimd, test
	TARGET_FLOAT.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/mgeneral-regs_1.c: New file.
	* gcc.target/aarch64/mgeneral-regs_2.c: New file.
	* gcc.target/aarch64/nofp_1.c: New file.


gcc/ChangeLog:

	* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
	and (no)crypto.
diff mbox

Patch

commit 298595e5254183de5b4c1cd2acaed43949b4dd30
Author: Alan Lawrence <alan.lawrence@arm.com>
Date:   Mon Jan 19 12:18:02 2015 +0000

    doc/invoke.texi, as approved, with whitespace.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e25bd62..0d62edf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12359,7 +12359,10 @@  Generate big-endian code.  This is the default when GCC is configured for an
 
 @item -mgeneral-regs-only
 @opindex mgeneral-regs-only
-Generate code which uses only the general registers.
+Generate code which uses only the general registers.  Equivalent to feature
+modifier @option{nofp} of @option{-march} or @option{-mcpu}, except that
+@option{-mgeneral-regs-only} takes precedence over any conflicting feature
+modifier regardless of sequence.
 
 @item -mlittle-endian
 @opindex mlittle-endian
@@ -12498,22 +12501,28 @@  over the appropriate part of this option.
 @subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
 @cindex @option{-march} feature modifiers
 @cindex @option{-mcpu} feature modifiers
-Feature modifiers used with @option{-march} and @option{-mcpu} can be one
-the following:
+Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
+the following, or their inverses @option{no@var{feature}}:
 
 @table @samp
 @item crc
 Enable CRC extension.
 @item crypto
-Enable Crypto extension.  This implies Advanced SIMD is enabled.
+Enable Crypto extension.  This also enables Advanced SIMD and floating-point
+instructions.
 @item fp
-Enable floating-point instructions.
+Enable floating-point instructions.  This is on by default for all possible
+values for options @option{-march} and @option{-mcpu}.
 @item simd
-Enable Advanced SIMD instructions.  This implies floating-point instructions
-are enabled.  This is the default for all current possible values for options
-@option{-march} and @option{-mcpu=}.
+Enable Advanced SIMD instructions.  This also enables floating-point
+instructions.  This is on by default for all possible values for options
+@option{-march} and @option{-mcpu}.
 @end table
 
+As stated above, @option{crypto} implies @option{simd} implies @option{fp}.
+Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+implies @option{nosimd} implies @option{nocrypto}.
+
 @node Adapteva Epiphany Options
 @subsection Adapteva Epiphany Options