From patchwork Fri Mar 26 17:15:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Makarov X-Patchwork-Id: 1458893 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=XzRzCrlJ; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F6TCG2sjHz9sS8 for ; Sat, 27 Mar 2021 04:16:09 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EADD23857C69; Fri, 26 Mar 2021 17:16:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EADD23857C69 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1616778967; bh=xO4xZ04jdBa6SS9DwhkT6Pe+lL7Gg9+jODGlH/F1a0s=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=XzRzCrlJWTKEkeCcnUBNo6QQkkt9+uCzHFx72hO1NU1gyqvk5HmXf2exVDuqIgyxc 2/38t91g4jjESMf1ZDzf05+a1wIv1B0V6B6k4QaP4ZB5imfuRIZTdmEj+s/nEQbGAr NVIDNMkjjnv0YY6onlF3bov5cexEN5LdbS45qSMU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTP id 52C563857C44 for ; Fri, 26 Mar 2021 17:16:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 52C563857C44 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-256-h5956RvkO8yAWSeOnJbKAA-1; Fri, 26 Mar 2021 13:15:59 -0400 X-MC-Unique: h5956RvkO8yAWSeOnJbKAA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1B24B1853039 for ; Fri, 26 Mar 2021 17:15:59 +0000 (UTC) Received: from [10.10.116.84] (ovpn-116-84.rdu2.redhat.com [10.10.116.84]) by smtp.corp.redhat.com (Postfix) with ESMTP id 97DFC614FB for ; Fri, 26 Mar 2021 17:15:58 +0000 (UTC) To: "gcc-patches@gcc.gnu.org" Subject: [committed] [PR99766] Consider relaxed memory associated more with memory instead of special memory Message-ID: <556041a6-0d43-b8b2-1214-37e2bf3107c4@redhat.com> Date: Fri, 26 Mar 2021 13:15:57 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Vladimir Makarov via Gcc-patches From: Vladimir Makarov Reply-To: Vladimir Makarov Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The following patch fixes   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766 The patch was successfully bootstrapped and tested on aarch64. commit 0d37e2d3ead072ba57e03fcb97a041504a22e721 Author: Vladimir Makarov Date: Fri Mar 26 17:09:24 2021 +0000 [PR99766] Consider relaxed memory associated more with memory instead of special memory. Relaxed memory should be considered more like memory then special memory. gcc/ChangeLog: PR target/99766 * ira-costs.c (record_reg_classes): Put case with CT_RELAXED_MEMORY adjacent to one with CT_MEMORY. * ira.c (ira_setup_alts): Ditto. * lra-constraints.c (process_alt_operands): Ditto. * recog.c (asm_operand_ok): Ditto. * reload.c (find_reloads): Ditto. gcc/testsuite/ChangeLog: PR target/99766 * g++.target/aarch64/sve/pr99766.C: New. diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index 7547f3e0f53..10727b5ff9e 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -773,6 +773,7 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, break; case CT_MEMORY: + case CT_RELAXED_MEMORY: /* Every MEM can be reloaded to fit. */ insn_allows_mem[i] = allows_mem[i] = 1; if (MEM_P (op)) @@ -780,7 +781,6 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, break; case CT_SPECIAL_MEMORY: - case CT_RELAXED_MEMORY: insn_allows_mem[i] = allows_mem[i] = 1; if (MEM_P (extract_mem_from_operand (op)) && constraint_satisfied_p (op, cn)) diff --git a/gcc/ira.c b/gcc/ira.c index 7e903289e79..b93588d8a9f 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -1871,10 +1871,10 @@ ira_setup_alts (rtx_insn *insn) goto op_success; case CT_MEMORY: + case CT_RELAXED_MEMORY: mem = op; /* Fall through. */ case CT_SPECIAL_MEMORY: - case CT_RELAXED_MEMORY: if (!mem) mem = extract_mem_from_operand (op); if (MEM_P (mem)) diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 861b5aad40b..9993065f8d6 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -2417,6 +2417,7 @@ process_alt_operands (int only_alternative) break; case CT_MEMORY: + case CT_RELAXED_MEMORY: if (MEM_P (op) && satisfies_memory_constraint_p (op, cn)) win = true; @@ -2459,7 +2460,6 @@ process_alt_operands (int only_alternative) break; case CT_SPECIAL_MEMORY: - case CT_RELAXED_MEMORY: if (satisfies_memory_constraint_p (op, cn)) win = true; else if (spilled_pseudo_p (op)) diff --git a/gcc/recog.c b/gcc/recog.c index ee143bc761e..eb617f11163 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -2267,10 +2267,10 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints) break; case CT_MEMORY: + case CT_RELAXED_MEMORY: mem = op; /* Fall through. */ case CT_SPECIAL_MEMORY: - case CT_RELAXED_MEMORY: /* Every memory operand can be reloaded to fit. */ if (!mem) mem = extract_mem_from_operand (op); diff --git a/gcc/reload.c b/gcc/reload.c index 7340125c441..461fd0272eb 100644 --- a/gcc/reload.c +++ b/gcc/reload.c @@ -3471,6 +3471,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known, break; case CT_MEMORY: + case CT_RELAXED_MEMORY: if (force_reload) break; if (constraint_satisfied_p (operand, cn)) @@ -3504,7 +3505,6 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known, break; case CT_SPECIAL_MEMORY: - case CT_RELAXED_MEMORY: if (force_reload) break; if (constraint_satisfied_p (operand, cn)) diff --git a/gcc/testsuite/g++.target/aarch64/sve/pr99766.C b/gcc/testsuite/g++.target/aarch64/sve/pr99766.C new file mode 100644 index 00000000000..0ca8aee5798 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/pr99766.C @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -march=armv8.2-a+sve" } */ +typedef float a __attribute__((__mode__(HF))); +typedef struct { + a b; + a c; +} d; +int e; +d *f, *g; +__fp16 h; +void j() { + for (int i;; ++i) { + auto l = &f[i]; + for (int k; k < e;) { + k = 0; + for (; k < e; ++k) + g[k].b = l[k].b * l[k].c; + } + for (int k; k < e; ++k) { + g[k].b *= h; + g[k].c *= h; + } + } +}