From patchwork Fri May 8 12:55:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 470031 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 824A8140077 for ; Fri, 8 May 2015 22:55:19 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=fXVkzq6M; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=C97bzvhM9l3tFRITL 9fKLk9aLSs5pX7uqz/o2wzqjgi8YR1JMBKO1FiYwE3iaZpbIO1Ky+SkyMvjNE6tx FZ7IxEKkUoyIOKE06wYAIHUfP3S6/k9GXUxtR2X72ZpmVbsPNfz3VxCEXn7RbUyn T9PSSkHkAq1f47KTTUeoiu+Meg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=H/SGC0fSEq008ZVn1JHKo6J aYjM=; b=fXVkzq6MySVJxdA5jyaeSPbgnxmuoNGx1R/tYgx5K7uYSdmc/KfmOp0 yJ0357Z+nIJy5My5ntJbEiA4odzoK/hazpe7wEJh0yt0ViWQA9ziZ4LyPhnlsj69 4AG+/E3IfpRsOTyDwU/aH/UNRss/1b96W2Lwxvz/jT2X93fdhKL0= Received: (qmail 18130 invoked by alias); 8 May 2015 12:55:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18117 invoked by uid 89); 8 May 2015 12:55:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, KAM_LOTSOFHASH, SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 08 May 2015 12:55:07 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-30.uk.mimecast.lan; Fri, 08 May 2015 13:55:04 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 8 May 2015 13:55:04 +0100 Message-ID: <554CB228.3070900@arm.com> Date: Fri, 08 May 2015 13:55:04 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: Joseph Myers CC: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft Subject: Re: [PATCH 5/14][AArch64] Add basic fp16 support References: <5537D500.4090308@arm.com> In-Reply-To: X-MC-Unique: PTkefiFYRNmo2fPgrX1cLA-1 X-IsSubscribed: yes Joseph Myers wrote: > > I'd think it would be desirable to share tests between ARM and AArch64 as > far as possible (where applicable to both - so not the tests for the > alternative format, and some of the gcc.target/arm/fp16-* tests using > scan-assembler might need adapting to work for AArch64). I agree the most desirable outcome is for the ACLE spec to be normalized between the two architectures! In the meantime this implements the specification that we have... I attach a new patch that adds common ARM / AArch64 tests in gcc.target/aarch64/fp16 (i.e. beside the shared gcc.target/aarch64/advsimd-intrinsics). I've adapted two of the previous tests such that they pass on both ARM and AArch64. I'd like to propose this as a patch 5a, and to drop those tests from the original patch 5. I'll follow-up with a sort-through of the ARM tests, moving only those that can be shared, in due course. Cheers, Alan diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_1.c b/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_1.c new file mode 100644 index 0000000000000000000000000000000000000000..a1c95fd28d14668c5cfa9cfb419c945878d7ac2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mfp16-format=ieee" {target "arm*-*-*"} } */ + +extern void abort (void); + +#define EPSILON 0.0001 + +int +main (int argc, char **argv) +{ + float f1 = 3.14159f; + float f2 = 2.718f; + /* This 'assembler' statement should be portable between ARM and AArch64. */ + asm volatile ("" : : : "memory"); + __fp16 in1 = f1; + __fp16 in2 = f2; + + /* Do the addition on __fp16's (implicitly converts both operands to + float32, adds, converts back to f16, then we convert back to f32). */ + __fp16 res1 = in1 + in2; + asm volatile ("" : : : "memory"); + float f_res_1 = res1; + + /* Do the addition on float32's (we convert both operands to f32, and add, + as above, but skip the final conversion f32 -> f16 -> f32). */ + float f1a = in1; + float f2a = in2; + float f_res_2 = f1a + f2a; + + if (__builtin_fabs (f_res_2 - f_res_1) > EPSILON) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_2.c b/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_2.c new file mode 100644 index 0000000000000000000000000000000000000000..6aa3e59c15e0eb85595871b47e8d8aa937cca47e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fp16/f16_convs_2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mfp16-format=ieee" {target "arm*-*-*"} } */ + +extern void abort (void); + +#define EPSILON 0.0001 + +int +main (int argc, char **argv) +{ + int i1 = 3; + int i2 = 2; + /* This 'assembler' should be portable across ARM and AArch64. */ + asm volatile ("" : : : "memory"); + + __fp16 in1 = i1; + __fp16 in2 = i2; + + /* Do the addition on __fp16's (implicitly converts both operands to + float32, adds, converts back to f16, then we convert to int). */ + __fp16 res1 = in1 + in2; + asm volatile ("" : : : "memory"); + int result1 = res1; + + /* Do the addition on int's (we convert both operands directly to int, add, + and we're done). */ + int result2 = ((int) in1) + ((int) in2); + + if (__builtin_abs (result2 - result1) > EPSILON) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/fp16.exp b/gcc/testsuite/gcc.target/aarch64/fp16/fp16.exp new file mode 100644 index 0000000000000000000000000000000000000000..7dc8d654a34004d280a1e9f6b9f39d868a60464a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fp16/fp16.exp @@ -0,0 +1,43 @@ +# Tests of 16-bit floating point (__fp16), for both ARM and AArch64. +# Copyright (C) 2015 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM or AArch64 target. +if {![istarget arm*-*-*] + && ![istarget aarch64*-*-*]} then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cC\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish