From patchwork Fri Apr 17 15:40:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 462140 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0D0E6140134 for ; Sat, 18 Apr 2015 01:40:42 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=hr9ydzny; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; q=dns; s=default; b=xwqO1+peHyz5kEidcLS+1IRM9TIWH Cf5qRIhfzA//znbGkNyxsPu+0Zb55BcSwC1iJEEeF9lcQ254WH3oa1NFBZlpqnWP y6eOr510xo8fBIin7B6f3FEJ/VBda+nsrIDnQnJF3fNqwKEolyz0nfIlzobLAmBq 8iLOdu8fOO9JZQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:in-reply-to :content-type; s=default; bh=C4OsHxwIB6mocB01Elw4/0EHCwo=; b=hr9 ydznyMun9lRwTtNWn6jTWs1VX/Bpfxy5/lFfBEuTKmCA/uqvRoFnYi9BaOHWnhtg wkqQ6QuipCc3TO91vC+uIVSYFBEZ+qKNWu+2NpZ64ylTrwce7usTakKghyj+u3Ub 49M9BXQAsCx+CKkYpzWiZ2Bcd5nPz+LmU2QV6AKU= Received: (qmail 84596 invoked by alias); 17 Apr 2015 15:40:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 84580 invoked by uid 89); 17 Apr 2015 15:40:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 17 Apr 2015 15:40:31 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-5.uk.mimecast.lan; Fri, 17 Apr 2015 16:40:28 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 17 Apr 2015 16:40:28 +0100 Message-ID: <5531296B.1030201@arm.com> Date: Fri, 17 Apr 2015 16:40:27 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 2/3][AArch64] Add vcond(u?)didi pattern In-Reply-To: <553128BB.90703@arm.com> X-MC-Unique: DeDVm4CnTBe9qCcywY2LPw-1 X-IsSubscribed: yes This just adds the necessary patterns used for comparisons of DImode vectors. Used as part of arm_neon.h, in next/final patch. Tested on aarch64-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_vcond_internal, vcond, vcondu,): Add DImode variant. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 52a1c3ba792adcaeaec9be4d8ada0f81bfa4714a..591740f5809d95f6f5502feda8599fd2958327bd 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2031,13 +2031,13 @@ }) (define_expand "aarch64_vcond_internal" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { rtx op1 = operands[1]; @@ -2339,13 +2339,13 @@ }) (define_expand "vcond" - [(set (match_operand:VALL 0 "register_operand") - (if_then_else:VALL + [(set (match_operand:VALLDI 0 "register_operand") + (if_then_else:VALLDI (match_operator 3 "comparison_operator" - [(match_operand:VALL 4 "register_operand") - (match_operand:VALL 5 "nonmemory_operand")]) - (match_operand:VALL 1 "nonmemory_operand") - (match_operand:VALL 2 "nonmemory_operand")))] + [(match_operand:VALLDI 4 "register_operand") + (match_operand:VALLDI 5 "nonmemory_operand")]) + (match_operand:VALLDI 1 "nonmemory_operand") + (match_operand:VALLDI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], @@ -2372,13 +2372,13 @@ }) (define_expand "vcondu" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1],