From patchwork Mon Jan 19 14:56:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 430554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9D90A14017F for ; Tue, 20 Jan 2015 01:56:59 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=QeDgRKrADIAj3nKfty2cq2dZVavqv5JD87qxBzg5c6lkXY a5GTD6UXQeTYauN3303QDBUNgQTzrZUW81TFGALnDFzIzclbLZrQ8/SvNqIL7/X4 Z/j50HHQWpwGIh9dBw4Qh2wOiZROfCs9AcT4/KJItMp0hp3QcKlYCRfo6heN4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=lgBxQZi4FHYmN1b3LSiSPMcOAdE=; b=GIiD3kO0xJhCcAj2mGsz izQvoWEAPPhD6b/8GCOkEAhPfRXJcvxPgeC4NayK/e5QEEM6ZsXxWmpuYbJSUcj5 RZLvw4vVX0/bUHM4NBZEQhH7JhjLBct5iuL0fQKQIn3nw4p6kSSd7wdrgEHf0P8y UUO7vlsRZ+/DD0H5FLNgdok= Received: (qmail 5187 invoked by alias); 19 Jan 2015 14:56:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5158 invoked by uid 89); 19 Jan 2015 14:56:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: foss-mx-na.foss.arm.com Received: from foss-mx-na.foss.arm.com (HELO foss-mx-na.foss.arm.com) (217.140.108.86) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Jan 2015 14:56:48 +0000 Received: from foss-smtp-na-1.foss.arm.com (unknown [10.80.61.8]) by foss-mx-na.foss.arm.com (Postfix) with ESMTP id E5358217 for ; Mon, 19 Jan 2015 08:56:39 -0600 (CST) Received: from collaborate-mta1.arm.com (highbank-bc01-b06.austin.arm.com [10.112.81.134]) by foss-smtp-na-1.foss.arm.com (Postfix) with ESMTP id A33EF5FAD7 for ; Mon, 19 Jan 2015 08:56:37 -0600 (CST) Received: from [10.1.209.42] (e105545-lin.cambridge.arm.com [10.1.209.42]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 3B56013F824 for ; Mon, 19 Jan 2015 08:56:37 -0600 (CST) Message-ID: <54BD1B26.9040100@arm.com> Date: Mon, 19 Jan 2015 14:56:38 +0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch ARM] PR target/64532 X-IsSubscribed: yes While looking at PR target/64532- I realized we haven't documented all the register constraints. I'm not documenting the other immediate constraints as it is not clear to me how much of that is actually useful yet and I don't have the time this afternoon to clean this up. Built documentation and looked at it. Applied. Ramana Ramana Radhakrishnan PR target/64532 * doc/md.texi (ARM Constraints): Document register constraints. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7bc7842..0050ba7 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1800,8 +1800,30 @@ Any const_double value. @item ARM family---@file{config/arm/constraints.md} @table @code + +@item h +In Thumb state, the core registers @code{r8}-@code{r15}. + +@item k +The stack pointer register. + +@item l +In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this +is an alias for the @code{r} constraint. + +@item t +VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values. + @item w -VFP floating-point register +VFP floating-point registers @code{d0}-@code{d31} and the appropriate +subset @code{d0}-@code{d15} based on command line options. +Used for 64 bit values only. Not valid for Thumb1. + +@item y +The iWMMX co-processor registers. + +@item z +The iWMMX GR registers. @item G The floating-point constant 0.0