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Wed, 07 Jul 2021 09:03:30 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16793Rwa32113042 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 Jul 2021 09:03:28 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9DD7B4C073; Wed, 7 Jul 2021 09:03:27 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C3FC4C062; Wed, 7 Jul 2021 09:03:26 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.34]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 7 Jul 2021 09:03:26 +0000 (GMT) To: GCC Patches Subject: [PATCH] rs6000: Support [u]mod3 for vector modulo insns Message-ID: <549ff7f8-690e-8710-3c63-76df21006704@linux.ibm.com> Date: Wed, 7 Jul 2021 17:03:23 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NY6JwTvgXSvPoLHwotFgbhh4mnOYoSmW X-Proofpoint-GUID: sNE3PUfu2Il7BbrKa-U4m4bgU_WF0Gp4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-07_05:2021-07-06, 2021-07-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107070052 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch is to make Power10 newly introduced vector modulo instructions exploited in vectorized loops, it just simply renames existing define_insns as standard pattern names. Is it ok for trunk? BR, Kewen ----- gcc/ChangeLog: * config/rs6000/rs6000-builtin.def (MODS_V2DI, MODS_V4SI, MODU_V2DI, MODU_V4SI): Adjust. * config/rs6000/vsx.md (mods_): Renamed to... (mod3): ... this. (modu_): Renamed to... (umod3): ... this. gcc/testsuite/ChangeLog: * gcc.target/powerpc/mod-vectorize.c: New test. --- gcc/config/rs6000/rs6000-builtin.def | 8 ++-- gcc/config/rs6000/vsx.md | 4 +- .../gcc.target/powerpc/mod-vectorize.c | 46 +++++++++++++++++++ 3 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/mod-vectorize.c diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index d7ce4de421e..592efe31b04 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -3012,10 +3012,10 @@ BU_P10V_AV_2 (DIVS_V4SI, "vdivsw", CONST, divv4si3) BU_P10V_AV_2 (DIVS_V2DI, "vdivsd", CONST, divv2di3) BU_P10V_AV_2 (DIVU_V4SI, "vdivuw", CONST, udivv4si3) BU_P10V_AV_2 (DIVU_V2DI, "vdivud", CONST, udivv2di3) -BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, mods_v2di) -BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, mods_v4si) -BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, modu_v2di) -BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, modu_v4si) +BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, modv2di3) +BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, modv4si3) +BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, umodv2di3) +BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, umodv4si3) BU_P10V_AV_2 (MULHS_V2DI, "vmulhsd", CONST, mulhs_v2di) BU_P10V_AV_2 (MULHS_V4SI, "vmulhsw", CONST, mulhs_v4si) BU_P10V_AV_2 (MULHU_V2DI, "vmulhud", CONST, mulhu_v2di) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f2260badf70..f622873d758 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6333,7 +6333,7 @@ (define_insn "udiv3" [(set_attr "type" "vecdiv") (set_attr "size" "")]) -(define_insn "mods_" +(define_insn "mod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] @@ -6342,7 +6342,7 @@ (define_insn "mods_" [(set_attr "type" "vecdiv") (set_attr "size" "")]) -(define_insn "modu_" +(define_insn "umod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] diff --git a/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c b/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c new file mode 100644 index 00000000000..4d4f5cd6446 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c @@ -0,0 +1,46 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ + +/* Test vectorizer can exploit ISA 3.1 instructions Vector Modulo + Signed/Unsigned Word/Doubleword for word/doubleword modulo operations. */ + +#define N 128 + +extern signed int si_a[N], si_b[N], si_c[N]; +extern unsigned int ui_a[N], ui_b[N], ui_c[N]; +extern signed long long sd_a[N], sd_b[N], sd_c[N]; +extern unsigned long long ud_a[N], ud_b[N], ud_c[N]; + +__attribute__ ((noipa)) void +test_si () +{ + for (int i = 0; i < N; i++) + si_c[i] = si_a[i] % si_b[i]; +} + +__attribute__ ((noipa)) void +test_ui () +{ + for (int i = 0; i < N; i++) + ui_c[i] = ui_a[i] % ui_b[i]; +} + +__attribute__ ((noipa)) void +test_sd () +{ + for (int i = 0; i < N; i++) + sd_c[i] = sd_a[i] % sd_b[i]; +} + +__attribute__ ((noipa)) void +test_ud () +{ + for (int i = 0; i < N; i++) + ud_c[i] = ud_a[i] % ud_b[i]; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ +/* { dg-final { scan-assembler-times {\mvmodsw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmoduw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmodsd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmodud\M} 1 } } */