From patchwork Fri Nov 14 15:46:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 410883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AA9701400D2 for ; Sat, 15 Nov 2014 02:46:22 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; q=dns; s=default; b=kqMsEAXS9XcWKat7h eRr4UtVyPwitl6MdnixQRNZYZSjB1UmbvcOYQHmImc9u5hjDJeHbx9v4S3+CGJPX dWRJOpXV2SsZIH/pwnZffsxQpRW8tWNpNoHyNEEOIELB1KF1IfmZiXA3a4+HlewA iQ8zeziNGdMuHTQP0MMbNGZVf4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; s=default; bh=JMCoHuMVGQnSi6+OmGpN/hl 4ZIY=; b=fuK9YJiZv940LmXEBwp6XgNvBKYuI9FqHvTaBlha+zyestzVdQZXfNJ 8veAm0WPylP5fXU1jZT1rjvb6BVDCmlezHZa/SLdwDDI8MxNlUPuuXqhrEHSOeBw mBwicmJlF5lb9mBgPjWaxDMpBj7n5UaSwexe/V3EDZYJQjhbW0Wg= Received: (qmail 2974 invoked by alias); 14 Nov 2014 15:46:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2963 invoked by uid 89); 14 Nov 2014 15:46:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Nov 2014 15:46:13 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 14 Nov 2014 15:46:10 +0000 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 14 Nov 2014 15:46:08 +0000 Message-ID: <546623BD.6020009@arm.com> Date: Fri, 14 Nov 2014 15:46:05 +0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH][AArch64]Add vec_shr pattern for 64-bit vectors using ush{l,r}; enable tests. References: <5466205F.80700@arm.com> In-Reply-To: <5466205F.80700@arm.com> X-MC-Unique: 114111415461005301 X-IsSubscribed: yes ...Patch attached... Alan Lawrence wrote: > Following recent vectorizer changes to reductions via shifts, AArch64 will now > reduce loops such as this > > unsigned char in[8] = {1, 3, 5, 7, 9, 11, 13, 15}; > > int > main (unsigned char argc, char **argv) > { > unsigned char prod = 1; > > /* Prevent constant propagation of the entire loop below. */ > asm volatile ("" : : : "memory"); > > for (unsigned char i = 0; i < 8; i++) > prod *= in[i]; > > if (prod != 17) > __builtin_printf("Failed %d\n", prod); > > return 0; > } > > using an 'ext' instruction from aarch64_expand_vec_perm_const: > > main: > adrp x0, .LANCHOR0 > movi v2.2s, 0 <=== note reg used here > ldr d1, [x0, #:lo12:.LANCHOR0] > ext v0.8b, v1.8b, v2.8b, #4 > mul v1.8b, v1.8b, v0.8b > ext v0.8b, v1.8b, v2.8b, #2 > mul v0.8b, v1.8b, v0.8b > ext v2.8b, v0.8b, v2.8b, #1 > mul v0.8b, v0.8b, v2.8b > umov w1, v0.b[0] > > The 'ext' works for both 64-bit vectors, and 128-bit vectors; but for 64-bit > vectors, we can do slightly better using ushr; this patch improves the above to: > > main: > adrp x0, .LANCHOR0 > ldr d0, [x0, #:lo12:.LANCHOR0] > ushr d1, d0, 32 > mul v0.8b, v0.8b, v1.8b > ushr d1, d0, 16 > mul v0.8b, v0.8b, v1.8b > ushr d1, d0, 8 > mul v0.8b, v0.8b, v1.8b > umov w1, v0.b[0] > ... > > Tested with bootstrap + check-gcc on aarch64-none-linux-gnu. > Cross-testing of check-gcc on aarch64_be-none-elf in progress. > > Ok if no regressions on big-endian? > > Cheers, > --Alan > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md (vec_shr): New. > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp > (check_effective_target_whole_vector_shift): Add aarch64{,_be}. > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index ef196e4b6fb39c0d2fd9ebfee76abab8369b1e92..397cb5186dd4ff000307f3b14bb4964d84c79469 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -779,6 +779,21 @@ } ) +;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero. +(define_insn "vec_shr_" + [(set (match_operand:VD 0 "register_operand" "=w") + (lshiftrt:VD (match_operand:VD 1 "register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + return "ushl %d0, %d1, %2"; + else + return "ushr %d0, %d1, %2"; + } + [(set_attr "type" "neon_shift_imm")] +) + (define_insn "aarch64_simd_vec_setv2di" [(set (match_operand:V2DI 0 "register_operand" "=w,w") (vec_merge:V2DI diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3361c2f9e8d98c5d1cc194617db6281127db2277..464c910777a53867110b462f121c02525d8dd140 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3335,6 +3335,7 @@ proc check_effective_target_vect_shift { } { proc check_effective_target_whole_vector_shift { } { if { [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget ia64-*-*] + || [istarget aarch64*-*-*] || ([check_effective_target_arm32] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*]