From patchwork Tue Nov 11 11:59:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 409407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 10C06140179 for ; Tue, 11 Nov 2014 23:00:01 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=xUotn5cenHCW3PUsZccY0BX0PSzQlpQQ9NMxi7sTdrV 1wmbY5fxtzc0u5Rpy73cAtJ/6SQKTdGbHMH55qx4CjSciTI1pS8PwxxH5NzMNRnH rhvYpp3y4xw38FGeMZ3riK6tFs0hm7Aq0E94r3RqeU0ucnwUaJbVb6LdsmWO1x0g = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=DDqNlUcGWgm07kvO5oCnqd2MIUg=; b=P9CZTZyAO8cf+OHC9 IHhCjCV/dEls8sWc6ey54sxwW8I8UCSsyyqCBh4kcRyLleLQP/EMpHE9Q+6NMHhz 9vyhHwLIlTej1ODIgZwsPMLFEG6a9VQGqYV0gW6gnuEfWC2RqpDq6Ryqt0qNlIfR 5j1rLsYoLNvGIUBw5nOYt6GKRo= Received: (qmail 5643 invoked by alias); 11 Nov 2014 11:59:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5624 invoked by uid 89); 11 Nov 2014 11:59:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 11 Nov 2014 11:59:53 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 11 Nov 2014 11:59:50 +0000 Received: from [10.1.207.43] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 11 Nov 2014 11:59:50 +0000 Message-ID: <5461FA36.5020600@arm.com> Date: Tue, 11 Nov 2014 11:59:50 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , Ramana Radhakrishnan Subject: [PATCH][ARM/AArch64] Improve modeled latency between FP operations and FP->GP register moves X-MC-Unique: 114111111595014501 X-IsSubscribed: yes Hi all, This patch models the latency of moves between FP and GP registers on the A15 and A57 a bit more accurately by splitting the reservations for FP->GP and GP->FP moves and adding an appropriate bypass. Bootstrapped and tested on arm-none-linux-gnueabihf and aarch64-none-linux-gnu. Ok for trunk? Thanks, Kyrill 2014-11-11 Kyrylo Tkachov * config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp): Split into... (cortex_a15_gp_to_vfp): ...This. (cortex_a15_fp_to_gp): ...And this. Define and comment bypass from vfp operations to fp->gp moves. commit c176d3e691f470598a02507fa75a8294da954c3f Author: Kyrylo Tkachov Date: Fri Jun 13 11:11:16 2014 +0100 [ARM/AArch64] Model FP->GP move stalls diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index 02d4a53..bc09cd6 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -655,10 +655,20 @@ (define_insn_reservation "cortex_a15_vfp_cpys" 4 (eq_attr "type" "fmov")) "ca15_issue1,ca15_cx_perm") -(define_insn_reservation "cortex_a15_vfp_to_from_gp" 5 +(define_insn_reservation "cortex_a15_gp_to_vfp" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "type" "f_mcr, f_mcrr, f_mrc, f_mrrc")) - "ca15_issue1,ca15_ls1+ca15_ls2") + (eq_attr "type" "f_mcr, f_mcrr")) + "ca15_issue1,ca15_ls") + +(define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5 + (and (eq_attr "tune" "cortexa15") + (eq_attr "type" "f_mrc, f_mrrc")) + "ca15_issue1,ca15_ls") + +;; Moves from floating point registers to general purpose registers +;; induce additional latency. +(define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp") + (define_insn_reservation "cortex_a15_vfp_ariths" 7 (and (eq_attr "tune" "cortexa15")