diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index c8c99f16113109f54e25fa282bbd44f65fcffc12..d7c148d2f977b73561992728ee084528029b4662 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -113,7 +113,9 @@ enum aarch64_type_qualifiers
   /* qualifier_const | qualifier_pointer | qualifier_map_mode  */
   qualifier_const_pointer_map_mode = 0x86,
   /* Polynomial types.  */
-  qualifier_poly = 0x100
+  qualifier_poly = 0x100,
+  /* Lane indices - must be in range, and flipped for bigendian.  */
+  qualifier_lane_index = 0x200
 };
 
 typedef struct
@@ -166,22 +168,26 @@ aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
 #define TYPES_TERNOP (aarch64_types_ternop_qualifiers)
 static enum aarch64_type_qualifiers
+aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_none, qualifier_none, qualifier_lane_index };
+#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
+static enum aarch64_type_qualifiers
 aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_unsigned,
       qualifier_unsigned, qualifier_unsigned };
 #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
 
 static enum aarch64_type_qualifiers
-aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none,
-      qualifier_none, qualifier_immediate };
-#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
+      qualifier_none, qualifier_lane_index };
+#define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers)
 
 static enum aarch64_type_qualifiers
-aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_immediate };
-#define TYPES_GETLANE (aarch64_types_getlane_qualifiers)
-#define TYPES_SHIFTIMM (aarch64_types_getlane_qualifiers)
+#define TYPES_GETREG (aarch64_types_binop_imm_qualifiers)
+#define TYPES_SHIFTIMM (aarch64_types_binop_imm_qualifiers)
 static enum aarch64_type_qualifiers
 aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_none, qualifier_immediate };
@@ -192,11 +198,11 @@ aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
 
 static enum aarch64_type_qualifiers
-aarch64_types_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+aarch64_types_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
-#define TYPES_SETLANE (aarch64_types_setlane_qualifiers)
-#define TYPES_SHIFTINSERT (aarch64_types_setlane_qualifiers)
-#define TYPES_SHIFTACC (aarch64_types_setlane_qualifiers)
+#define TYPES_SETREG (aarch64_types_ternop_imm_qualifiers)
+#define TYPES_SHIFTINSERT (aarch64_types_ternop_imm_qualifiers)
+#define TYPES_SHIFTACC (aarch64_types_ternop_imm_qualifiers)
 
 static enum aarch64_type_qualifiers
 aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
@@ -771,6 +777,7 @@ typedef enum
 {
   SIMD_ARG_COPY_TO_REG,
   SIMD_ARG_CONSTANT,
+  SIMD_ARG_LANE_INDEX,
   SIMD_ARG_STOP
 } builtin_simd_arg;
 
@@ -814,6 +821,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
 		op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
 	      break;
 
+	    case SIMD_ARG_LANE_INDEX:
+	      /* Must be a previous operand into which this is an index.  */
+	      gcc_assert (argc > 0);
+	      if (CONST_INT_P (op[argc]))
+	        {
+	          enum machine_mode vmode = mode[argc - 1];
+	          aarch64_simd_lane_bounds (op[argc],
+					    0, GET_MODE_NUNITS (vmode));
+	          /* Keep to GCC-vector-extension lane indices in the RTL.  */
+	          op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc])));
+	        }
+	      /* Fall through - if the lane index isn't a constant then
+	         the next case will error.  */
 	    case SIMD_ARG_CONSTANT:
 	      if (!(*insn_data[icode].operand[argc + have_retval].predicate)
 		  (op[argc], mode[argc]))
@@ -922,7 +942,9 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
       int operands_k = k - is_void;
       int expr_args_k = k - 1;
 
-      if (d->qualifiers[qualifiers_k] & qualifier_immediate)
+      if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
+	args[k] = SIMD_ARG_LANE_INDEX;
+      else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
 	args[k] = SIMD_ARG_CONSTANT;
       else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
 	{
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 62b7f3357d12f2a4a483588e3ccf027c3f957c20..10bf67eb7c87346199c3c88253a2331720a380ef 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -47,7 +47,8 @@
   VAR1 (UNOP, addp, 0, di)
   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
 
-  BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
+  /* be_checked_get_lane does its own lane swapping, so not a lane index.  */
+  BUILTIN_VALL (GETREG, be_checked_get_lane, 0)
 
   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
@@ -64,17 +65,17 @@
   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
 
   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
-  BUILTIN_VDC (GETLANE, get_dregoi, 0)
-  BUILTIN_VDC (GETLANE, get_dregci, 0)
-  BUILTIN_VDC (GETLANE, get_dregxi, 0)
+  BUILTIN_VDC (GETREG, get_dregoi, 0)
+  BUILTIN_VDC (GETREG, get_dregci, 0)
+  BUILTIN_VDC (GETREG, get_dregxi, 0)
   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (GETLANE, get_qregoi, 0)
-  BUILTIN_VQ (GETLANE, get_qregci, 0)
-  BUILTIN_VQ (GETLANE, get_qregxi, 0)
+  BUILTIN_VQ (GETREG, get_qregoi, 0)
+  BUILTIN_VQ (GETREG, get_qregci, 0)
+  BUILTIN_VQ (GETREG, get_qregxi, 0)
   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (SETLANE, set_qregoi, 0)
-  BUILTIN_VQ (SETLANE, set_qregci, 0)
-  BUILTIN_VQ (SETLANE, set_qregxi, 0)
+  BUILTIN_VQ (SETREG, set_qregoi, 0)
+  BUILTIN_VQ (SETREG, set_qregci, 0)
+  BUILTIN_VQ (SETREG, set_qregxi, 0)
   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
@@ -142,43 +143,44 @@
   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 
-  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0)
-  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0)
-  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0)
-  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
-  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0)
-  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0)
-  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0)
-  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
+  /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>.  */
+  BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
+  BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
+  /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>.  */
+  BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
+  BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 
+  BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
+  BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
+  BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
+  BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
+  BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
+  BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
+  BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
+
   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
-  BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
-  BUILTIN_VSD_HSI (TERNOP, sqdmull_laneq, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
-  BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
-  BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
-  BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_laneq, 0)
-  BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
-  BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_laneq, 0)
-  BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
-  BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
+  BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
+  BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
+  BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
+  BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
 
   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
   /* Implemented by aarch64_<sur>shl<mode>.  */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 578760a4b3ce002b982f1704e2e72b12b2e88957..ddef1f0de6246d5e21186e26a68a43cda67f99ba 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2759,41 +2759,7 @@
 
 ;; sq<r>dmulh_lane
 
-(define_expand "aarch64_sqdmulh_lane<mode>"
-  [(match_operand:VDQHS 0 "register_operand" "")
-   (match_operand:VDQHS 1 "register_operand" "")
-   (match_operand:<VCOND> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
-     emit_insn (gen_aarch64_sqdmulh_lane<mode>_internal (operands[0],
-                                                         operands[1],
-                                                         operands[2],
-                                                         operands[3]));
-     DONE;
-  }
-)
-
-(define_expand "aarch64_sqrdmulh_lane<mode>"
-  [(match_operand:VDQHS 0 "register_operand" "")
-   (match_operand:VDQHS 1 "register_operand" "")
-   (match_operand:<VCOND> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
-     emit_insn (gen_aarch64_sqrdmulh_lane<mode>_internal (operands[0],
-                                                          operands[1],
-                                                          operands[2],
-                                                          operands[3]));
-     DONE;
-  }
-)
-
-(define_insn "aarch64_sq<r>dmulh_lane<mode>_internal"
+(define_insn "aarch64_sq<r>dmulh_lane<mode>"
   [(set (match_operand:VDQHS 0 "register_operand" "=w")
         (unspec:VDQHS
 	  [(match_operand:VDQHS 1 "register_operand" "w")
@@ -2803,47 +2769,12 @@
 	 VQDMULH))]
   "TARGET_SIMD"
   "*
-   aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
    return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
 )
 
-(define_expand "aarch64_sqdmulh_laneq<mode>"
-  [(match_operand:VSDQ_HSI 0 "register_operand" "")
-   (match_operand:VSDQ_HSI 1 "register_operand" "")
-   (match_operand:<VCONQ> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
-     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
-     emit_insn (gen_aarch64_sqdmulh_laneq<mode>_internal (operands[0],
-                                                          operands[1],
-                                                          operands[2],
-                                                          operands[3]));
-     DONE;
-   }
-)
-
-(define_expand "aarch64_sqrdmulh_laneq<mode>"
-  [(match_operand:VSDQ_HSI 0 "register_operand" "")
-   (match_operand:VSDQ_HSI 1 "register_operand" "")
-   (match_operand:<VCONQ> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-     aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
-     operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
-     emit_insn (gen_aarch64_sqrdmulh_laneq<mode>_internal (operands[0],
-                                                           operands[1],
-                                                           operands[2],
-                                                           operands[3]));
-     DONE;
-   }
-)
-
-(define_insn "aarch64_sq<r>dmulh_laneq<mode>_internal"
+(define_insn "aarch64_sq<r>dmulh_laneq<mode>"
   [(set (match_operand:VDQHS 0 "register_operand" "=w")
         (unspec:VDQHS
 	  [(match_operand:VDQHS 1 "register_operand" "w")
@@ -2858,41 +2789,7 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
 )
 
-(define_expand "aarch64_sqdmulh_lane<mode>"
-  [(match_operand:SD_HSI 0 "register_operand" "")
-   (match_operand:SD_HSI 1 "register_operand" "")
-   (match_operand:<VCOND> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-    aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
-    emit_insn (gen_aarch64_sqdmulh_lane<mode>_internal (operands[0],
-                                                        operands[1],
-                                                        operands[2],
-                                                        operands[3]));
-    DONE;
-  }
-)
-
-(define_expand "aarch64_sqrdmulh_lane<mode>"
-  [(match_operand:SD_HSI 0 "register_operand" "")
-   (match_operand:SD_HSI 1 "register_operand" "")
-   (match_operand:<VCOND> 2 "register_operand" "")
-   (match_operand:SI 3 "immediate_operand" "")]
-  "TARGET_SIMD"
-  {
-    aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-    operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
-    emit_insn (gen_aarch64_sqrdmulh_lane<mode>_internal (operands[0],
-                                                         operands[1],
-                                                         operands[2],
-                                                         operands[3]));
-    DONE;
-  }
-)
-
-(define_insn "aarch64_sq<r>dmulh_lane<mode>_internal"
+(define_insn "aarch64_sq<r>dmulh_lane<mode>"
   [(set (match_operand:SD_HSI 0 "register_operand" "=w")
         (unspec:SD_HSI
 	  [(match_operand:SD_HSI 1 "register_operand" "w")
@@ -2907,7 +2804,7 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
 )
 
-(define_insn "aarch64_sq<r>dmulh_laneq<mode>_internal"
+(define_insn "aarch64_sq<r>dmulh_laneq<mode>"
   [(set (match_operand:SD_HSI 0 "register_operand" "=w")
         (unspec:SD_HSI
 	  [(match_operand:SD_HSI 1 "register_operand" "w")
@@ -2942,7 +2839,7 @@
 
 ;; vqdml[sa]l_lane
 
-(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal"
+(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (SBINQOPS:<VWIDE>
 	  (match_operand:<VWIDE> 1 "register_operand" "0")
@@ -2966,7 +2863,7 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal"
+(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (SBINQOPS:<VWIDE>
 	  (match_operand:<VWIDE> 1 "register_operand" "0")
@@ -2990,7 +2887,7 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal"
+(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (SBINQOPS:<VWIDE>
 	  (match_operand:<VWIDE> 1 "register_operand" "0")
@@ -3013,7 +2910,7 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal"
+(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (SBINQOPS:<VWIDE>
 	  (match_operand:<VWIDE> 1 "register_operand" "0")
@@ -3036,70 +2933,6 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_expand "aarch64_sqdmlal_lane<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:<VWIDE> 1 "register_operand" "0")
-   (match_operand:VSD_HSI 2 "register_operand" "w")
-   (match_operand:<VCOND> 3 "register_operand" "<vwx>")
-   (match_operand:SI 4 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
-  emit_insn (gen_aarch64_sqdmlal_lane<mode>_internal (operands[0], operands[1],
-						      operands[2], operands[3],
-						      operands[4]));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlal_laneq<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:<VWIDE> 1 "register_operand" "0")
-   (match_operand:VSD_HSI 2 "register_operand" "w")
-   (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
-   (match_operand:SI 4 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
-  emit_insn (gen_aarch64_sqdmlal_laneq<mode>_internal (operands[0], operands[1],
-						      operands[2], operands[3],
-						      operands[4]));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlsl_lane<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:<VWIDE> 1 "register_operand" "0")
-   (match_operand:VSD_HSI 2 "register_operand" "w")
-   (match_operand:<VCOND> 3 "register_operand" "<vwx>")
-   (match_operand:SI 4 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
-  emit_insn (gen_aarch64_sqdmlsl_lane<mode>_internal (operands[0], operands[1],
-						      operands[2], operands[3],
-						      operands[4]));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlsl_laneq<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:<VWIDE> 1 "register_operand" "0")
-   (match_operand:VSD_HSI 2 "register_operand" "w")
-   (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
-   (match_operand:SI 4 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
-  emit_insn (gen_aarch64_sqdmlsl_laneq<mode>_internal (operands[0], operands[1],
-						      operands[2], operands[3],
-						      operands[4]));
-  DONE;
-})
-
 ;; vqdml[sa]l_n
 
 (define_insn "aarch64_sqdml<SBINQOPS:as>l_n<mode>"
@@ -3230,8 +3063,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
   emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       operands[4], p));
@@ -3247,8 +3078,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
   emit_insn (gen_aarch64_sqdmlal2_laneq<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       operands[4], p));
@@ -3264,8 +3093,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
   emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       operands[4], p));
@@ -3281,8 +3108,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
   emit_insn (gen_aarch64_sqdmlsl2_laneq<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       operands[4], p));
@@ -3354,7 +3179,7 @@
 
 ;; vqdmull_lane
 
-(define_insn "aarch64_sqdmull_lane<mode>_internal"
+(define_insn "aarch64_sqdmull_lane<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (ss_ashift:<VWIDE>
 	     (mult:<VWIDE>
@@ -3375,7 +3200,7 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdmull_laneq<mode>_internal"
+(define_insn "aarch64_sqdmull_laneq<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (ss_ashift:<VWIDE>
 	     (mult:<VWIDE>
@@ -3396,7 +3221,7 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdmull_lane<mode>_internal"
+(define_insn "aarch64_sqdmull_lane<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (ss_ashift:<VWIDE>
 	     (mult:<VWIDE>
@@ -3416,7 +3241,7 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
 )
 
-(define_insn "aarch64_sqdmull_laneq<mode>_internal"
+(define_insn "aarch64_sqdmull_laneq<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
         (ss_ashift:<VWIDE>
 	     (mult:<VWIDE>
@@ -3436,34 +3261,6 @@
   [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
 )
 
-(define_expand "aarch64_sqdmull_lane<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:VSD_HSI 1 "register_operand" "w")
-   (match_operand:<VCOND> 2 "register_operand" "<vwx>")
-   (match_operand:SI 3 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
-  emit_insn (gen_aarch64_sqdmull_lane<mode>_internal (operands[0], operands[1],
-						      operands[2], operands[3]));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmull_laneq<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand" "=w")
-   (match_operand:VSD_HSI 1 "register_operand" "w")
-   (match_operand:<VCONQ> 2 "register_operand" "<vwx>")
-   (match_operand:SI 3 "immediate_operand" "i")]
-  "TARGET_SIMD"
-{
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
-  emit_insn (gen_aarch64_sqdmull_laneq<mode>_internal
-	       (operands[0], operands[1], operands[2], operands[3]));
-  DONE;
-})
-
 ;; vqdmull_n
 
 (define_insn "aarch64_sqdmull_n<mode>"
@@ -3573,8 +3370,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
-  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
   emit_insn (gen_aarch64_sqdmull2_lane<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       p));
@@ -3589,8 +3384,6 @@
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
-  operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
   emit_insn (gen_aarch64_sqdmull2_laneq<mode>_internal (operands[0], operands[1],
 						       operands[2], operands[3],
 						       p));
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index bd82d1c56dcb54efd504fa5259121bf5de5764e9..0679a83d4ee4a01d5ad2eb4ad16c16cc96fe3fb5 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8197,7 +8197,7 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
   lane = INTVAL (operand);
 
   if (lane < low || lane >= high)
-    error ("lane out of range");
+    error ("lane %ld out of range %ld - %ld", lane, low, high - 1);
 }
 
 /* Emit code to place a AdvSIMD pair result in memory locations (with equal
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..5efac337bdb4df9a5c6bfd5ad337879f792acc69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..47239e95b50ad6307b8deb58c503153d9590bab8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlal_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlal_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7ae9762a529125f0d47c74f6abcb625d114fffeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c
@@ -0,0 +1,22 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+  int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlal_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlal_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..11f69488eb9788e4f7943a81b44c7e7195b7512a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c
@@ -0,0 +1,22 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+  int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ee74b00e9b26bc82010dc843998af04f8c34a8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_lane_s16 (int32x4_a, int16x4_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_lane_s16 (int32x4_a, int16x4_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..810c349dceb45d32e3dfeae6f07b6772f815080a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlal_lane_s32 (int64x2_a, int32x2_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlal_lane_s32 (int64x2_a, int32x2_b, int32x2_c, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..70998af8c669b7817437d1c4c21930dc08df5dab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlal_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlal_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6ed0ecd8d8ef523973a9755d8c61da197bdee613
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlal_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..1e9ac16118176a5e8691b1b6647a65834db6b8a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  int16_t int16_b = 0x5678;
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int32_t int32_a = 0xdeadbeef;
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlalh_lane_s16 (int32_a, int16_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlalh_lane_s16 (int32_a, int16_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..43e656a4c5e599a0ca8904457448de7f2a1e3e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  int64_t int64_a = 0x1111222233334444LL;
+  int32_t int32_b = 0xcafebabe;
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlals_lane_s32 (int64_a, int32_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlals_lane_s32 (int64_a, int32_b, int32x2_c, 2);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..72c5d228aa79d0a787c29ed5ea86c370d89b3fec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0d87f69efe2390eefce7d9870990464ccd23c0a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsl_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsl_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7328e6265b516235ea0218a373663077fe074ce0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c
@@ -0,0 +1,22 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+  int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlsl_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlsl_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8af0fa51d6cf0747fe1923f1e3bb88ad804bc7ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c
@@ -0,0 +1,22 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+  int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..c969550c4c3d1d30ec6bd97f9f3175079e407e3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_lane_s16 (int32x4_a, int16x4_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_lane_s16 (int32x4_a, int16x4_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8419a2a7c21059e98c76dd7bfc49e75b6e95bf4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsl_lane_s32 (int64x2_a, int32x2_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsl_lane_s32 (int64x2_a, int32x2_b, int32x2_c, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a02498fbee7063b0df278cf402ddd92399a7508
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlsl_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmlsl_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..40d155f0dcf942a7d1daa71e39f3db6882943238
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_c = vcombine_u64 (base_c, base_a);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c);
+  int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlsl_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e25976685f7ea92b736f48be3690c4fcdd3dbc67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  int16_t int16_b = 0x5678;
+  int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c);
+  int32_t int32_a = 0xdeadbeef;
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlslh_lane_s16 (int32_a, int16_b, int16x4_c, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmlslh_lane_s16 (int32_a, int16_b, int16x4_c, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf9163009b8528b019bb431909ce6e53de9a9429
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  int64_t int64_a = 0x1111222233334444LL;
+  int32_t int32_b = 0xcafebabe;
+  int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsls_lane_s32 (int64_a, int32_b, int32x2_c, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmlsls_lane_s32 (int64_a, int32_b, int32x2_c, 2);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..bbd04fe65b66d319f2faef660df15bd141b160a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulh_lane_s16 (int16x4_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulh_lane_s16 (int16x4_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..4f442f8beba051ee6c3b2f6253d837cab715524b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulh_lane_s32 (int32x2_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulh_lane_s32 (int32x2_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..f6f4a2eb9fe9a8b4ca73d160c1f5d7e0305d3796
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmulh_laneq_s16 (int16x4_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmulh_laneq_s16 (int16x4_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e5ed97f3dbbf7e27155db53ec114aef7bfc7e3d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulh_laneq_s32 (int32x2_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulh_laneq_s32 (int32x2_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..35713a0108b0791d4ebd33d4a61a99fa48161083
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16_t int16_a = 0x1234;
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhh_lane_s16 (int16_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhh_lane_s16 (int16_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8acb26059195c011657f62e499fb3fafb2107461
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhq_lane_s16 (int16x8_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhq_lane_s16 (int16x8_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..791759e564066bada7fe655b5534b70a12f5d05d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulhq_lane_s32 (int32x4_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulhq_lane_s32 (int32x4_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..f1f9844f4033d347b027de81f091fe84da59a740
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmulhq_laneq_s16 (int16x8_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmulhq_laneq_s16 (int16x8_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..d222a9e159ac2282259bb45a62b272c761fe65cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhq_laneq_s32 (int32x4_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmulhq_laneq_s32 (int32x4_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..d3dc792547039c6f9e7b89034bb47323f9524fd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32_t int32_a = 0xdeadbeef;
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulhs_lane_s32 (int32_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulhs_lane_s32 (int32_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..b1a8babe14b39384fb26c41d90faeb04348dfd4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_high_lane_s16 (int16x8_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_high_lane_s16 (int16x8_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..ae1edae7c85f32e6e0ef8a45741140b1dbd1b7f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmull_high_lane_s32 (int32x4_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmull_high_lane_s32 (int32x4_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8a97e82d33c481577490b48719add6fbdf40ae60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmull_high_laneq_s16 (int16x8_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmull_high_laneq_s16 (int16x8_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e92b4cb7c28c843ae9eb1b7f62ba51b0dd9fdd38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_high_laneq_s32 (int32x4_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_high_laneq_s32 (int32x4_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..a9c237ae087e5dec7ec062da6de5626355a9a737
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_lane_s16 (int16x4_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_lane_s16 (int16x4_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..49a782cb9e80e5bce6ce0f531da126d77c86be65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmull_lane_s32 (int32x2_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmull_lane_s32 (int32x2_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0a5ba28bbe34113e2f998d1452eb443ecd5788e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmull_laneq_s16 (int16x4_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqdmull_laneq_s16 (int16x4_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..88fcf8d164c68be73c444d9fd5f12cb3661bf1ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_laneq_s32 (int32x2_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmull_laneq_s32 (int32x2_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..28cf52a9133a678b950b59a7d30e7ad50f1d2b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16_t int16_a = 0x1234;
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmullh_lane_s16 (int16_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqdmullh_lane_s16 (int16_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0d3d9dd76deb969d43c4e137c1dc0c5268b81565
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32_t int32_a = 0xdeadbeef;
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulls_lane_s32 (int32_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqdmulls_lane_s32 (int32_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..afc6633b9d92205573f5a31067e5ca50397b8e86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulh_lane_s16 (int16x4_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulh_lane_s16 (int16x4_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..c74397772ce2d498826f91e7ae647a430888e15f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulh_lane_s32 (int32x2_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulh_lane_s32 (int32x2_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..3d69dac0e13b5a9669f96fd2272447802969fef2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqrdmulh_laneq_s16 (int16x4_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqrdmulh_laneq_s16 (int16x4_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..98b85ebbb1bb4b95b7e16d8b35098c22c5d3f0f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulh_laneq_s32 (int32x2_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulh_laneq_s32 (int32x2_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..1abad3fa85fe2d430904895220c3830267ef379c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int16_t int16_a = 0x1234;
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhh_lane_s16 (int16_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhh_lane_s16 (int16_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..d9e39fa03ff4e029d23a1ded1d77441142744a51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhq_lane_s16 (int16x8_a, int16x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhq_lane_s16 (int16x8_a, int16x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..186a0917e8e25608e1ec36a4f89750f3273e9b8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulhq_lane_s32 (int32x4_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulhq_lane_s32 (int32x4_a, int32x2_b, 2);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0479b2aaac144b3a254e2dbc03312290dd5e5c1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a);
+  int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqrdmulhq_laneq_s16 (int16x8_a, int16x8_b, -1);
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  vqrdmulhq_laneq_s16 (int16x8_a, int16x8_b, 8);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..30b6272956eabbc6ec5a3a87ae88ab8e0b5bc1bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL);
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  uint64x2_t baseq_a = vcombine_u64 (base_a, base_b);
+  uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL);
+  uint64x2_t baseq_b = vcombine_u64 (base_b, base_c);
+  int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a);
+  int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b);
+
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhq_laneq_s32 (int32x4_a, int32x4_b, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  vqrdmulhq_laneq_s32 (int32x4_a, int32x4_b, 4);
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..ee901124e06c0e7b25b8febe0abe0b57e7c6ecdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c99" } */
+#include <arm_neon.h>
+
+int
+main (int argc, char **argv)
+{
+  uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL);
+  int32_t int32_a = 0xdeadbeef;
+  int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b);
+
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulhs_lane_s32 (int32_a, int32x2_b, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  vqrdmulhs_lane_s32 (int32_a, int32x2_b, 2);
+}
\ No newline at end of file