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Fri, 24 Oct 2014 12:12:50 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 24 Oct 2014 13:12:47 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 24 Oct 2014 13:12:47 +0100 Message-ID: <544A423E.8060606@arm.com> Date: Fri, 24 Oct 2014 13:12:46 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" , David Edelsohn , Segher Boessenkool Subject: Re: [PATCH 10/11][RS6000] Migrate reduction optabs to reduc_..._scal In-Reply-To: <544A40D1.1040605@arm.com> X-MC-Unique: 114102413124709601 X-IsSubscribed: yes Ooops, attached. commit e48d59399722ce8316d4b1b4f28b40d87b1193fa Author: Alan Lawrence Date: Tue Oct 7 15:28:47 2014 +0100 PowerPC v2 (but not paired.md) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 02ea142..92bb5d0 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2596,35 +2596,22 @@ operands[3] = gen_reg_rtx (GET_MODE (operands[0])); }) -(define_expand "reduc_splus_" - [(set (match_operand:VIshort 0 "register_operand" "=v") +(define_expand "reduc_plus_scal_" + [(set (match_operand: 0 "register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")] UNSPEC_REDUC_PLUS))] "TARGET_ALTIVEC" { rtx vzero = gen_reg_rtx (V4SImode); rtx vtmp1 = gen_reg_rtx (V4SImode); - rtx dest = gen_lowpart (V4SImode, operands[0]); + rtx vtmp2 = gen_reg_rtx (mode); + rtx dest = gen_lowpart (V4SImode, vtmp2); + HOST_WIDE_INT last_elem = GET_MODE_NUNITS (mode) - 1; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); - DONE; -}) - -(define_expand "reduc_uplus_v16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_REDUC_PLUS))] - "TARGET_ALTIVEC" -{ - rtx vzero = gen_reg_rtx (V4SImode); - rtx vtmp1 = gen_reg_rtx (V4SImode); - rtx dest = gen_lowpart (V4SImode, operands[0]); - - emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); - emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); - emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); + rs6000_expand_vector_extract (operands[0], vtmp2, last_elem); DONE; }) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 237724e..54b18aa 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -81,7 +81,7 @@ ;; Vector reduction code iterators (define_code_iterator VEC_reduc [plus smin smax]) -(define_code_attr VEC_reduc_name [(plus "splus") +(define_code_attr VEC_reduc_name [(plus "plus") (smin "smin") (smax "smax")]) @@ -1077,18 +1077,20 @@ ;; Vector reduction expanders for VSX -(define_expand "reduc__v2df" - [(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "") - (VEC_reduc:V2DF - (vec_concat:V2DF - (vec_select:DF - (match_operand:V2DF 1 "vfloat_operand" "") - (parallel [(const_int 1)])) - (vec_select:DF - (match_dup 1) - (parallel [(const_int 0)]))) - (match_dup 1))) - (clobber (match_scratch:V2DF 2 ""))])] +(define_expand "reduc__scal_v2df" + [(parallel [(set (match_operand:DF 0 "vfloat_operand" "") + (vec_select:DF + (VEC_reduc:V2DF + (vec_concat:V2DF + (vec_select:DF + (match_operand:V2DF 1 "vfloat_operand" "") + (parallel [(const_int 1)])) + (vec_select:DF + (match_dup 1) + (parallel [(const_int 0)]))) + (match_dup 1)) + (parallel [(const_int 1)]))) + (clobber (match_scratch:DF 2 ""))])] "VECTOR_UNIT_VSX_P (V2DFmode)" "") @@ -1099,13 +1101,16 @@ ; is to allow us to use a code iterator, but not completely list all of the ; vector rotates, etc. to prevent canonicalization -(define_expand "reduc__v4sf" - [(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "") - (VEC_reduc:V4SF - (unspec:V4SF [(const_int 0)] UNSPEC_REDUC) - (match_operand:V4SF 1 "vfloat_operand" ""))) +(define_expand "reduc__scal_v4sf" + [(parallel [(set (match_operand:SF 0 "vfloat_operand" "") + (vec_select:SF + (VEC_reduc:V4SF + (unspec:V4SF [(const_int 0)] UNSPEC_REDUC) + (match_operand:V4SF 1 "vfloat_operand" "")) + (parallel [(const_int 3)]))) (clobber (match_scratch:V4SF 2 "")) - (clobber (match_scratch:V4SF 3 ""))])] + (clobber (match_scratch:V4SF 3 "")) + (clobber (match_scratch:V4SF 4 ""))])] "VECTOR_UNIT_VSX_P (V4SFmode)" "")