From patchwork Wed Sep 5 11:51:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 966341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-485177-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="O3fndHmH"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4252C94TSsz9s5c for ; Wed, 5 Sep 2018 21:53:09 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type; q=dns; s=default; b=pKi+0/3K7OW0nyHlOYgCpKral9T+O sRUJDp+WHz+1F0mXorojWzpoT9vgHsG70baxpxnogNAJDZAWJKnyHV7BbbuwN0aF 20RgVng6XQltOQpIpkE+5MhgWWQlk+Rzuick2FBsy03SNgTqRgOl+p+l0pR6UAKX e0cOJQwXCeBH40= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type; s=default; bh=X11d5rQ5Qh79sQt58UPI719QDlE=; b=O3f ndHmHrZPaMvnjCq45vFZ3Khs6qI7lLTkUrIMmUeVOj5nMxDqnP3HCBSHbJiHG8Sn lAyoPUwF1MEKLnNfM7phkxEybNGKjzFaQKiRWPwDFdFnTiPB87iqLuhAOctmkHrU gm+w4KWt7gOKgcL9nnzD/IWhZR3hWu9Uk++BGys4= Received: (qmail 95701 invoked by alias); 5 Sep 2018 11:51:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 95616 invoked by uid 89); 5 Sep 2018 11:51:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.2 spammy=begins, ICEs, ira, ices X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Sep 2018 11:51:39 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fxWLR-00067y-Hg for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 07:51:38 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:45550) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fxWLR-00066w-9U for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 07:51:37 -0400 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=svr-ies-mbx-01.mgc.mentorg.com) by relay1.mentorg.com with esmtps (TLSv1.2:ECDHE-RSA-AES256-SHA384:256) id 1fxWLQ-0005r1-DJ from Andrew_Stubbs@mentor.com for gcc-patches@gcc.gnu.org; Wed, 05 Sep 2018 04:51:36 -0700 Received: from build6-trusty-cs.sje.mentorg.com (137.202.0.90) by svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Wed, 5 Sep 2018 12:51:32 +0100 From: To: Subject: [PATCH 16/25] Fix IRA ICE. Date: Wed, 5 Sep 2018 12:51:17 +0100 Message-ID: <54304bb66c95238afe5a603eff894caf56ac19ca.1536144068.git.ams@codesourcery.com> In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 The IRA pass makes an assumption that any pseudos created after the pass begins were created explicitly by the pass itself and therefore will have corresponding entries in its other tables. The GCN back-end, however, often creates additional pseudos, in expand patterns, to represent the necessary EXEC value, and these break IRA's assumption and cause ICEs. This patch simply has IRA skip unknown pseudos, and the problem goes away. Presumably, it's not ideal that these registers have not been processed by IRA, but it does not appear to do any real harm. 2018-09-05 Andrew Stubbs gcc/ * ira.c (setup_preferred_alternate_classes_for_new_pseudos): Skip pseudos not created by this pass. (move_unallocated_pseudos): Likewise. --- gcc/ira.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/gcc/ira.c b/gcc/ira.c index def194a..e0c293c 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -2769,7 +2769,12 @@ setup_preferred_alternate_classes_for_new_pseudos (int start) for (i = start; i < max_regno; i++) { old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); - ira_assert (i != old_regno); + + /* Skip any new pseudos not created directly by this pass. + gen_move_insn can do this on AMD GCN, for example. */ + if (i == old_regno) + continue; + setup_reg_classes (i, reg_preferred_class (old_regno), reg_alternate_class (old_regno), reg_allocno_class (old_regno)); @@ -5054,6 +5059,12 @@ move_unallocated_pseudos (void) { int idx = i - first_moveable_pseudo; rtx other_reg = pseudo_replaced_reg[idx]; + + /* Skip any new pseudos not created directly by find_moveable_pseudos. + gen_move_insn can do this on AMD GCN, for example. */ + if (!other_reg) + continue; + rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); /* The use must follow all definitions of OTHER_REG, so we can insert the new definition immediately after any of them. */