From patchwork Thu Sep 18 13:02:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 390823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C51BE1401AF for ; Thu, 18 Sep 2014 23:02:28 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=gT8kzEPAdALHgAAU4 bwrv+Sjm0C7BfLVVM12268cxctSOVha6IWfuQLMSv2y3EKJoo4z3EwHGuPfuwPd2 EocrTg2BE7JH9Dxr3K+tQQfkfvslSjUeMYlZra37ZBRtLsywiqk5Ii49lkS4bibB 1tIN7HSHrkm2N9OHHdVF9mG1j0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=Fz4R7NwCT8glblOENK4ZMXK 3gmg=; b=FwtvcUBieFENBWGKIxNqaQBWsbcYRHjI+34pPpXqAKrO0ArsJjZMJOO ee3qEbB5XmFRgkUSDLEk3ruhwLNP4TQvHcz3DrDEAP22bohOuGgxX5sOORGQUNIh GRVzdGo+UkTRZS7x4PV1X+itoQci84uZHgHlR8FO0uaBXGDYgjhw= Received: (qmail 20838 invoked by alias); 18 Sep 2014 13:02:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20829 invoked by uid 89); 18 Sep 2014 13:02:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 18 Sep 2014 13:02:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 18 Sep 2014 14:02:18 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Sep 2014 14:02:15 +0100 Message-ID: <541AD7D7.5000308@arm.com> Date: Thu, 18 Sep 2014 14:02:15 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Steve Ellcey , Eric Christopher Subject: [PATCH 16 / 14+2][MIPS] Remove vec_shl and (hopefully) fix vec_shr References: <541AC4D2.9040901@arm.com> In-Reply-To: <541AC4D2.9040901@arm.com> X-MC-Unique: 114091814021801401 X-IsSubscribed: yes Patch 12 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01475.html) will break bigendian targets implementing vec_shr. This is a MIPS parallel of patch 13 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01477.html) for AArch64; the idea is that vec_shr should be unaffected on little-endian, but reversed (to be the same as the old vec_shl) if big-endian. Manual inspection of assembler output looks to do the right sort of thing on mips and mips64, but I haven't been able to run any testcases so this is not definitive. I'm hoping it is nonetheless helpful as a starting point! gcc/ChangeLog: * config/mips/loongson.md (unspec): Remove UNSPEC_LOONGSON_DSLL. (vec_shl_): Remove. (vec_shr_): Reverse shift if BYTES_BIG_ENDIAN. diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md index 474033d1e2c244d3b70ad5ed630ab9f29d5fd5f6..dcba23440a5cb8cf0f2063ee15fbcf9d2a579714 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson.md @@ -39,7 +39,6 @@ UNSPEC_LOONGSON_PUNPCKL UNSPEC_LOONGSON_PADDD UNSPEC_LOONGSON_PSUBD - UNSPEC_LOONGSON_DSLL UNSPEC_LOONGSON_DSRL ]) @@ -834,22 +833,18 @@ }) ;; Whole vector shifts, used for reduction epilogues. -(define_insn "vec_shl_" - [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSLL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsll\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - (define_insn "vec_shr_" [(set (match_operand:VWHBDI 0 "register_operand" "=f") (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")] UNSPEC_LOONGSON_DSRL))] "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsrl\t%0,%1,%2" + { + if (BYTES_BIG_ENDIAN) + return "dsll\t%0,%1,%2"; + else + return "dsrl\t%0,%1,%2"; + } [(set_attr "type" "fcvt")]) (define_expand "reduc_uplus_"