From patchwork Mon Sep 8 16:25:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 386982 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A633114017B for ; Tue, 9 Sep 2014 02:25:59 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; q=dns; s=default; b=GG7rrgMcRfxlZ7YCh d2Q55aDyQ0CO8O7EuTrrx6enfYP7wWOiGP/GsvaVzC6TBisLF0VYq+aLnhsfio5p NvIOgD0ZfDYjZMzxHco5jyvDqLBjwUPTiAnhdP4XEbsOKhGNDMCG9EEBx5NWNKEW v+4xzf5EGao2qa0e3uMPTlUG8Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; s=default; bh=TQaBvO5Yxs6HGeipLzIOJ8Q johU=; b=Ga9yqONDYMY0awBBnbh6bK8a89nFpe2Uisve3PWlLRDxkZuSmzpoekm JJg8XtCBtKB6RpHzLgmZoL8Adbu3sut9rPnAskxCRhM8glaewdQBS2iDWTkSXkft wA7jj9CgA0dJ6llNWFIMKe64hsAhFGyrcgjXJsQqeERwJ1iRyALs= Received: (qmail 4926 invoked by alias); 8 Sep 2014 16:25:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4916 invoked by uid 89); 8 Sep 2014 16:25:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 08 Sep 2014 16:25:50 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 08 Sep 2014 17:25:47 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 8 Sep 2014 17:25:45 +0100 Message-ID: <540DD888.4030406@arm.com> Date: Mon, 08 Sep 2014 17:25:44 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 2/2][AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic References: <540DD708.4080804@arm.com> In-Reply-To: <540DD708.4080804@arm.com> X-MC-Unique: 114090817254712501 X-IsSubscribed: yes Similarly, the ushr_n_u64 and ushrd_n_u64 intrinsics, allow to perform an unsigned-shift-right of a 64-bit value by 64 places. This is not supported by the standard lshr pattern, which masks the shift amount with 63. However, a shift-by-64 always produces zero, so this patch moves in a constant 0 rather than outputting a shift instruction. Cross-tested on aarch64-none-elf and aarch64_be-none-elf, with test coverage provided by gcc.target/aarch64/ushr64_1.c . gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift by 64 by moving const0_rtx. (aarch64_ushr_simddi): Delete. * config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64. Alan Lawrence wrote: > The sshr_n_64 intrinsics allow performing a signed shift right by 64 places. The > standard ashrdi3 pattern masks the sign amount with 63, so cannot be used. > However, such a shift fills the result by the sign bit, which is identical to > shifting right by 63. This patch just simplifies the code to shift by 63 > instead, which allows to remove an UNSPEC and insn previously dedicated to this > case. > > Cross-tested on aarch64-none-elf and aarch64_be-none-elf, with test coverage > provided by gcc.target/aarch64/sshr64_1.c . > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64. > > * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change shift > amount to 63 if was 64. > (aarch64_sshr_simddi): Remove. > > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f9ace6d195a7f7db74751c79c316fdce3696abf6..d493054b703c5698b771ce32d613e28d7c7b7b49 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -739,24 +739,13 @@ "TARGET_SIMD" { if (INTVAL (operands[2]) == 64) - emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1])); + emit_move_insn (operands[0], const0_rtx); else emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2])); DONE; } ) -;; SIMD shift by 64. This pattern is a special case as standard pattern does -;; not handle NEON shifts by 64. -(define_insn "aarch64_ushr_simddi" - [(set (match_operand:DI 0 "register_operand" "=w") - (unspec:DI - [(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))] - "TARGET_SIMD" - "ushr\t%d0, %d1, 64" - [(set_attr "type" "neon_shift_imm")] -) - (define_expand "vec_set" [(match_operand:VQ_S 0 "register_operand") (match_operand: 1 "register_operand") diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3c51fd367e954d513aac1180ec4025f15d46c87e..736da80b2705d02793433e6cdbcd422bfecc76f4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -111,7 +111,6 @@ UNSPEC_TLS UNSPEC_TLSDESC UNSPEC_USHL_2S - UNSPEC_USHR64 UNSPEC_VSTRUCTDUMMY UNSPEC_SP_SET UNSPEC_SP_TEST diff --git a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c index b1c741dac3125d97ca3440329ecb32c7d2889d81..ee494894f6fb6f9cb354d836121a7bc6d0d2cdb6 100644 --- a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c @@ -42,7 +42,6 @@ test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected) return vshrd_n_u64 (passed, 0) != expected; } -/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */ /* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2) || \ (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */ /* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */