@@ -739,24 +739,13 @@
"TARGET_SIMD"
{
if (INTVAL (operands[2]) == 64)
- emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1]));
+ emit_move_insn (operands[0], const0_rtx);
else
emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
DONE;
}
)
-;; SIMD shift by 64. This pattern is a special case as standard pattern does
-;; not handle NEON shifts by 64.
-(define_insn "aarch64_ushr_simddi"
- [(set (match_operand:DI 0 "register_operand" "=w")
- (unspec:DI
- [(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))]
- "TARGET_SIMD"
- "ushr\t%d0, %d1, 64"
- [(set_attr "type" "neon_shift_imm")]
-)
-
(define_expand "vec_set<mode>"
[(match_operand:VQ_S 0 "register_operand")
(match_operand:<VEL> 1 "register_operand")
@@ -111,7 +111,6 @@
UNSPEC_TLS
UNSPEC_TLSDESC
UNSPEC_USHL_2S
- UNSPEC_USHR64
UNSPEC_VSTRUCTDUMMY
UNSPEC_SP_SET
UNSPEC_SP_TEST
@@ -42,7 +42,6 @@ test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
return vshrd_n_u64 (passed, 0) != expected;
}
-/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
/* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2) || \
(scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
/* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */