From patchwork Tue Aug 12 14:55:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 379389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7CD2A14008C for ; Wed, 13 Aug 2014 00:55:33 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; q=dns; s=default; b=HzwFf+idU3U1bW979 KvsbyQ5t0ZN1xA9QKHOLcGCr7r3pN0267lN7zJolug6jcQsR0A6lZNmHcw9yBPDE ex2QQ7gmWTx2jziLi5oOQeeYUfC879Ulkat8B+y8svjcBpIxnhhbtvvD6K17JFNH pj2WviJl/wtKjr7BXvyRlUHYlM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; s=default; bh=fSd3PWNFmuwrpiQfEgo2s/R y0FM=; b=F3brk108T7Vu4ieXkxKVeDIipShiys4QRsW0Eee8o5KavbZdx2TxGKB 5AxUTOgjVO0FSGO8uOITSHMu+YlIILsNHOnFgFd9uFdpBVxaFFFrOitDjqmySts2 fLIgOxnaFsIfpzp2ZdUF625VZ7HkewV+6xDL7hBGVzut9nPSBhkY= Received: (qmail 15765 invoked by alias); 12 Aug 2014 14:55:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15735 invoked by uid 89); 12 Aug 2014 14:55:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Aug 2014 14:55:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 12 Aug 2014 15:55:17 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 12 Aug 2014 15:55:17 +0100 Message-ID: <53EA2AD4.1070403@arm.com> Date: Tue, 12 Aug 2014 15:55:16 +0100 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON References: <53EA26D1.4010506@arm.com> <53EA2932.2050606@arm.com> In-Reply-To: <53EA2932.2050606@arm.com> X-MC-Unique: 114081215551704901 X-IsSubscribed: yes ...patch attached... Alan Lawrence wrote: > [When I wrote that xor was broken on GPRs and this fixes it, I meant > xor_one_cmpl rather than xor, sorry!] > > The pattern for xor_one_cmpl never matched, due to the action of > combine_simplify_rtx; hence, separate this pattern out from that for ORN/BIC. > > ORN/BIC have equivalent SIMD-reg variants, so add those for the benefit of > values in vector registers (e.g. passed as [u]int64x1_t parameters). > > EON does not have a SIMD-reg variant; however, it seems better to split it (to > XOR + NOT) than to move both arguments to GPRs, perform EON, and move the result > back. > > gcc/ChangeLog: > > * config/aarch64/aarch64.c (_one_cmpl3): > Reparameterize to... > (_one_cmpl3): with extra SIMD-register variant. > (xor_one_cmpl3): New define_insn_and_split. > > * config/aarch64/iterators.md (NLOGICAL): New define_code_iterator. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/eon_1.c: New test. > > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8eaf1be3ba6e39ca00a2ae3905e84375b354ccd8..2b9cc29148e699b8b6839b6e1294d0eebcad9001 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2757,14 +2757,36 @@ [(set_attr "type" "logic_shift_imm")] ) -(define_insn "*_one_cmpl3" - [(set (match_operand:GPI 0 "register_operand" "=r") - (LOGICAL:GPI (not:GPI - (match_operand:GPI 1 "register_operand" "r")) - (match_operand:GPI 2 "register_operand" "r")))] +;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b). + +(define_insn "*_one_cmpl3" + [(set (match_operand:GPI 0 "register_operand" "=r,w") + (NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand" "r,w")) + (match_operand:GPI 2 "register_operand" "r,w")))] + "" + "@ + \\t%0, %2, %1 + \\t%0., %2., %1." + [(set_attr "type" "logic_reg,neon_logic") + (set_attr "simd" "*,yes")] +) + +;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)). +;; eon does not operate on SIMD registers so the vector variant must be split. +(define_insn_and_split "*xor_one_cmpl3" + [(set (match_operand:GPI 0 "register_operand" "=r,w") + (not:GPI (xor:GPI (match_operand:GPI 1 "register_operand" "r,?w") + (match_operand:GPI 2 "register_operand" "r,w"))))] + "" + "eon\\t%0, %1, %2" ;; For GPR registers (only). + "reload_completed && (which_alternative == 1)" ;; For SIMD registers. + [(set (match_operand:GPI 0 "register_operand" "=w") + (xor:GPI (match_operand:GPI 1 "register_operand" "w") + (match_operand:GPI 2 "register_operand" "w"))) + (set (match_dup 0) (not:GPI (match_dup 0)))] "" - "\\t%0, %2, %1" - [(set_attr "type" "logic_reg")] + [(set_attr "type" "logic_reg,multiple") + (set_attr "simd" "*,yes")] ) (define_insn "*and_one_cmpl3_compare0" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index b7f1d5709eeda0362117f7de3800b99048352225..da8bea2ea4f9e2cc8abae5375b908a247a7edc2f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -668,6 +668,9 @@ ;; Code iterator for logical operations (define_code_iterator LOGICAL [and ior xor]) +;; Code iterator for logical operations whose :nlogical works on SIMD registers. +(define_code_iterator NLOGICAL [and ior]) + ;; Code iterator for sign/zero extension (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) diff --git a/gcc/testsuite/gcc.target/aarch64/eon_1.c b/gcc/testsuite/gcc.target/aarch64/eon_1.c new file mode 100644 index 0000000000000000000000000000000000000000..dcdf3b4d052e034e0475028b238bdff0105d4c44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/eon_1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "\tf?mov\t" } } */ + +typedef long long int64_t; +typedef int64_t int64x1_t __attribute__ ((__vector_size__ (8))); + +/* { dg-final { scan-assembler-times "\\teon\\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */ + +int64_t +test_eon (int64_t a, int64_t b) +{ + return a ^ ~b; +} + +/* { dg-final { scan-assembler-times "\\tmvn\\tx\[0-9\]+, x\[0-9\]+" 1 } } */ +int64_t +test_not (int64_t a) +{ + return ~a; +} + +/* There is no eon for SIMD regs; we prefer eor+mvn to mov+mov+eon+mov. */ + +/* { dg-final { scan-assembler-times "\\teor\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ +/* { dg-final { scan-assembler-times "\\tmvn\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 2 } } */ +int64x1_t +test_vec_eon (int64x1_t a, int64x1_t b) +{ + return a ^ ~b; +} + +int64x1_t +test_vec_not (int64x1_t a) +{ + return ~a; +} +