From patchwork Mon Aug 4 12:22:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 376260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 82100140090 for ; Mon, 4 Aug 2014 22:22:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=AOJq38HmNqHdTJeSMwECkDwqMsj3q1G6TIgmQ2/ViOt 8OP8f0eTEinBvp4VZ2769/9xMIENAiPWXunRnEQ26YSw/Ft1KuauXSZ7TYwvBaia w7GtolDkDIbJdGAcmICvxlEiPvjtSiAKtG85AdYHBu1HD8EdTswVMFtu2FqvCtgo = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=gibm+Sqd5E5XAO5NxXP/PgLOJz8=; b=XylbyUtKcYh2WyqoD DAiMKf5Gv8UcypjBj5vR6OQZQaDooVNhLnjEvvKs0hxPkMAYzs+uBA2pDKapOyHC VUszfrMxcXcaZCmblyPtgLFSH3AeAWmkizYwl/WBV6d1p8g1QM/BGxtZGOJ1OjYi GqpnF/FNCeFqYroJleCoSNym5Q= Received: (qmail 962 invoked by alias); 4 Aug 2014 12:22:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 943 invoked by uid 89); 4 Aug 2014 12:22:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 04 Aug 2014 12:22:46 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 04 Aug 2014 13:22:43 +0100 Received: from [10.1.208.24] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Aug 2014 13:22:41 +0100 Message-ID: <53DF7B10.6080101@arm.com> Date: Mon, 04 Aug 2014 13:22:40 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] Adjust clz, rbit and rev patterns for -mrestrict-it X-MC-Unique: 114080413224308401 X-IsSubscribed: yes Hi all, While working on another patch and looking at the rbit and clz patterns, I noticed that in aarch32 the relevant patterns are not adjusted for -mrestrict-it. A program like: int foo (int a, int b) { if (a + 5 == b) return __builtin_ctz (a); return 1; } compiled with -march=armv8-a -mthumb could generate clz and rbit instructions inside an IT block, thus earning an assembler warning. Whilst there I also noticed that the output templates for the arm_rev pattern have a %? that is used to print out condition codes during predication but the pattern is not marked as predicable. So I set the predicable attribute there and adjusted it for -mrestrict-it while at it. Ok for trunk? 2014-08-04 Kyrylo Tkachov * config/arm/arm.md (clzsi2): Set predicable_short_it attr to no. (rbitsi2): Likewise. (*arm_rev): Set predicable and predicable_short_it attributes. commit 1ea85f18ff46fa985ba79e6e64715ecf855751c3 Author: Kyrylo Tkachov Date: Wed Jul 9 16:38:45 2014 +0100 [ARM] Handle IT deprecation for clz, rbit, rev diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 916d552..3e1a1bb 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10662,6 +10662,7 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) (define_insn "rbitsi2" @@ -10670,6 +10671,7 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) (define_expand "ctzsi2" @@ -10829,6 +10831,8 @@ rev%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") + (set_attr "predicable_short_it" "no") (set_attr "type" "rev")] )