From patchwork Mon Jun 9 10:06:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 357377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B128314007B for ; Mon, 9 Jun 2014 20:06:28 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=fMnT1kjYtWqsaNWj6Z9l9gvMW+a2XBy/boiM2+Fx0bZ F6LGYZd0bLyDctkAeWjxF3SNDtCT3H863Jxihq4b5nlJu81ieldgl+hzrtGSre4V 3I4n6iZaEjnfv2kECheVy1yWxEhsHhLYRdmh+2Jk7P4hpzTpz+1c/S5THj9lcycw = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=Q+4jvGyLgcuaIKfKdG1+CtpQpUE=; b=QVL/WPr2ST7rCxDxt rnWQliow+/7plnc0CAQD3P1zIWLz/Ef/GoLzSmZQSNnaSpK3ZJTVxfHE4vCiMiPn W8R2O30aAZC3VfhTTSgomnIizAZ5fep7vHfONrXQh3rPNtVlLHWz1Du6xIq0c5CD rn9S9gFkgumjJMTjY1xbg3quO4= Received: (qmail 18067 invoked by alias); 9 Jun 2014 10:06:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18057 invoked by uid 89); 9 Jun 2014 10:06:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Jun 2014 10:06:19 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 09 Jun 2014 11:06:16 +0100 Received: from [10.1.208.24] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 9 Jun 2014 11:06:11 +0100 Message-ID: <53958717.8060306@arm.com> Date: Mon, 09 Jun 2014 11:06:15 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM][doc] Improve description of AArch32 CRC32 intrinsics X-MC-Unique: 114060911061608401 X-IsSubscribed: yes Hi all, The ACLE intrinsics documentation for arm can be improved a bit. Since there are potentially other ACLE intrinsics besides the CRC32 ones in the future, I moved the comment about their availability into the CRC32 intrinsics subsection. I removed the comment about the instruction form expected for AArch64 since that is a separate port and should be documented in the AArch64 section. Tested by building the PDF doc and looking at it. I think this should go for 4.9 as well as trunk as it is a clarification. Ok? Thanks, Kyrill 2014-06-09 Kyrylo Tkachov * doc/arm-acle-intrinsics.texi: Specify when CRC32 intrinsics are available. Simplify description of __crc32d and __crc32cd intrinsics. * doc/extend.texi (ARM ACLE Intrinsics): Remove comment about CRC32 availability. diff --git a/gcc/doc/arm-acle-intrinsics.texi b/gcc/doc/arm-acle-intrinsics.texi index e68f4cd..8c5523e 100644 --- a/gcc/doc/arm-acle-intrinsics.texi +++ b/gcc/doc/arm-acle-intrinsics.texi @@ -4,6 +4,10 @@ @subsubsection CRC32 intrinsics +These intrinsics are available when the CRC32 architecture extension is +specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when +the target processor specified with @option{-mcpu} supports it. + @itemize @bullet @item uint32_t __crc32b (uint32_t, uint8_t) @*@emph{Form of expected instruction(s):} @code{crc32b @var{r0}, @var{r0}, @var{r0}} @@ -25,8 +29,7 @@ @itemize @bullet @item uint32_t __crc32d (uint32_t, uint64_t) @*@emph{Form of expected instruction(s):} Two @code{crc32w @var{r0}, @var{r0}, @var{r0}} -instructions for AArch32. One @code{crc32w @var{w0}, @var{w0}, @var{x0}} instruction for -AArch64. +instructions. @end itemize @itemize @bullet @@ -50,6 +53,5 @@ AArch64. @itemize @bullet @item uint32_t __crc32cd (uint32_t, uint64_t) @*@emph{Form of expected instruction(s):} Two @code{crc32cw @var{r0}, @var{r0}, @var{r0}} -instructions for AArch32. One @code{crc32cw @var{w0}, @var{w0}, @var{x0}} instruction for -AArch64. +instructions. @end itemize diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index a2fe619..a68020a 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -10519,9 +10519,6 @@ when the @option{-mfpu=neon} switch is used: @node ARM ACLE Intrinsics @subsection ARM ACLE Intrinsics -These built-in intrinsics for the ARMv8-A CRC32 extension are available when -the @option{-march=armv8-a+crc} switch is used: - @include arm-acle-intrinsics.texi @node AVR Built-in Functions