Message ID | 538CA76E.1060200@arm.com |
---|---|
State | New |
Headers | show |
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 120ada9..9b46f58 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2014-06-02 Marcus Shawcroft <marcus.shawcroft@arm.com> + + * config/aarch64/aarch64.md (set_fpcr): Drop ISB after FPCR write. + 2014-06-01 Uros Bizjak <ubizjak@gmail.com> * config/i386/constraints.md (Bw): Rename from 'w'. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index fec2ea8..6e605c1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3904,7 +3904,7 @@ (define_insn "set_fpcr" [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPCR)] "" - "msr\\tfpcr, %0\;isb" + "msr\\tfpcr, %0" [(set_attr "type" "mrs")]) ;; Read Floating-point Control Register.