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[58.6.183.210]) by mx.google.com with ESMTPSA id yv7sm13586215pac.33.2014.05.14.17.10.19 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 14 May 2014 17:10:19 -0700 (PDT) Message-ID: <537405E1.8020000@linaro.org> Date: Thu, 15 May 2014 10:10:09 +1000 From: Kugan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [RFC][AArch64] Remove CORE_REGS form reg_class References: <5373FA98.1050806@linaro.org> In-Reply-To: <5373FA98.1050806@linaro.org> X-Forwarded-Message-Id: <5373FA98.1050806@linaro.org> X-IsSubscribed: yes Hi All, AAarch64 back-end defines GENERAL_REGS and CORE_REGS with the same set of register. Is there any reason why we need this? target hooks like aarch64_register_move_cost doesn’t handle CORE_REGS. In addition, IRA cost calculation also has logics like make common class biggest of best and alternate; this might get confused with this. Attached RFC patch removes it. regression tested for aarch64-none-linux-gnu on qemu-aarch64 with now new regression. Is this OK ? Thanks, Kugan gcc/ 2014-05-14 Kugan Vivekanandarajah * config/aarch64/aarch64.c (aarch64_regno_regclass) : Change CORE_REGS to GENERAL_REGS. (aarch64_secondary_reload) : LikeWise. (aarch64_class_max_nregs) : Remove CORE_REGS. * config/aarch64/aarch64.h (enum reg_class) : Remove CORE_REGS. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : LikeWise. (INDEX_REG_CLASS) : Change CORE_REGS to GENERAL_REGS. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index a3147ee..eee36ba 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3951,7 +3951,7 @@ enum reg_class aarch64_regno_regclass (unsigned regno) { if (GP_REGNUM_P (regno)) - return CORE_REGS; + return GENERAL_REGS; if (regno == SP_REGNUM) return STACK_REG; @@ -4102,12 +4102,12 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, /* A TFmode or TImode memory access should be handled via an FP_REGS because AArch64 has richer addressing modes for LDR/STR instructions than LDP/STP instructions. */ - if (!TARGET_GENERAL_REGS_ONLY && rclass == CORE_REGS + if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS && GET_MODE_SIZE (mode) == 16 && MEM_P (x)) return FP_REGS; if (rclass == FP_REGS && (mode == TImode || mode == TFmode) && CONSTANT_P(x)) - return CORE_REGS; + return GENERAL_REGS; return NO_REGS; } @@ -4239,7 +4239,6 @@ aarch64_class_max_nregs (reg_class_t regclass, enum machine_mode mode) { switch (regclass) { - case CORE_REGS: case POINTER_REGS: case GENERAL_REGS: case ALL_REGS: diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 7962aa4..3455ecc 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -409,7 +409,6 @@ extern unsigned long aarch64_tune_flags; enum reg_class { NO_REGS, - CORE_REGS, GENERAL_REGS, STACK_REG, POINTER_REGS, @@ -424,7 +423,6 @@ enum reg_class #define REG_CLASS_NAMES \ { \ "NO_REGS", \ - "CORE_REGS", \ "GENERAL_REGS", \ "STACK_REG", \ "POINTER_REGS", \ @@ -436,7 +434,6 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0x7fffffff, 0x00000000, 0x00000003 }, /* CORE_REGS */ \ { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ @@ -447,7 +444,7 @@ enum reg_class #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) -#define INDEX_REG_CLASS CORE_REGS +#define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS POINTER_REGS /* Register pairs used to eliminate unneeded registers that point into