From patchwork Tue Apr 29 08:59:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom de Vries X-Patchwork-Id: 343694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 39F6B1400DE for ; Tue, 29 Apr 2014 19:00:06 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=LRR6nQd6gkA5iEegi mEZthhpOBTy5pRb6ovLxCPuIaDISwlWFZW9cEMG/tnmMp9ciPkqyqmSnQBcwc8aR FD/UfEPSddM2WnKZRX7pYYQPrySBqSNThatW9/OyG+bKmfAdEST2ze8BPPopG657 nyv46nN8GHzsrH0+lEenZ1HLJk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=uduzST2KdOZ1WfvN/BKe/4w QLR8=; b=nOM59/5ydgeGq2rjhYUj6eV4MlPK8Dq0mb0lCJf7nvVEMCdHuK3VqjX 0/UDw3VSH3haajUWIGDM4+Mn8g+uIYh8/FxkBfgcqPEqM/bOBdb6Np3vuJ327gZZ lk9a0mthbkep/lL6GHLC1dNlvq5/jHpeNPHC/uJFFGUcdcYrW2sY= Received: (qmail 21587 invoked by alias); 29 Apr 2014 08:59:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21571 invoked by uid 89); 29 Apr 2014 08:59:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_STOCKGEN autolearn=no version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 29 Apr 2014 08:59:54 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1Wf3tF-0007ER-OZ from Tom_deVries@mentor.com ; Tue, 29 Apr 2014 01:59:49 -0700 Received: from SVR-IES-FEM-02.mgc.mentorg.com ([137.202.0.106]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 29 Apr 2014 01:59:49 -0700 Received: from [127.0.0.1] (137.202.0.76) by SVR-IES-FEM-02.mgc.mentorg.com (137.202.0.106) with Microsoft SMTP Server id 14.2.247.3; Tue, 29 Apr 2014 09:59:47 +0100 Message-ID: <535F6A00.9050906@mentor.com> Date: Tue, 29 Apr 2014 10:59:44 +0200 From: Tom de Vries User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Eric Botcazou CC: , , Richard Earnshaw Subject: Re: Add post_expand_call_insn hook References: <534ED7BC.50300@mentor.com> <5356853D.8050905@mentor.com> <5357BB57.1090506@mentor.com> <2772726.PK66iRW19H@polaris> In-Reply-To: <2772726.PK66iRW19H@polaris> On 24-04-14 17:13, Eric Botcazou wrote: >> The hook is called right after expansion of calls, and allows a target to do >> additional processing, such as f.i. adding clobbers to >> CALL_INSN_FUNCTION_USAGE. >> >> Instead of using the hook, we could add code to the preparation statements >> operand of the different call expands, but that requires those expands not >> to use the rtl template, and generate all the rtl through c code. Which >> requires a rewrite of the call expands in case of Aarch64. > > If Aarch64 is the only problematic back-end, then it should be changed to do > what the other back-ends already do to use use_reg. IMO adding such a bogus > hook should be the very last resort solution. > Eric, I've written this concept patch, which tries to address the same problem, but in a different (and I hope more generic) way. It adds a post-emission C-code operand to define_expand. As an example of how this could be useful, for the define_expand of call and call_value in the arm target, I'm using the new operand to do the post-emit call processing done currently in arm_emit_call_insn. This allows us to eliminate the call_internal and call_value_internal define_expands, and simplifies the call and call_value define_expands. Any comments? Thanks, - Tom diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 74645ee..506791a 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -126,7 +126,7 @@ extern int arm_const_double_inline_cost (rtx); extern bool arm_const_double_by_parts (rtx); extern bool arm_const_double_by_immediates (rtx); extern const char *fp_immediate_constant (rtx); -extern void arm_emit_call_insn (rtx, rtx); +extern void arm_post_emit_call_insn (rtx, rtx); extern const char *output_call (rtx *); extern const char *output_call_mem (rtx *); void arm_emit_movpair (rtx, rtx); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 09b5c52..e36deac 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -17602,16 +17602,14 @@ vfp_emit_fstmd (int base_reg, int count) return count * 8; } -/* Emit a call instruction with pattern PAT. ADDR is the address of - the call target. */ +/* Process a call instruction with pattern PAT after emission. ADDR is the + address of the call target. */ void -arm_emit_call_insn (rtx pat, rtx addr) +arm_post_emit_call_insn (rtx pat, rtx addr) { rtx insn; - insn = emit_call_insn (pat); - /* The PIC register is live on entry to VxWorks PIC PLT entries. If the call might use such an entry, add a use of the PIC register to the instruction's CALL_INSN_FUNCTION_USAGE. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8a949b9..45019ae 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -9082,7 +9082,7 @@ "TARGET_EITHER" " { - rtx callee, pat; + rtx callee; /* In an untyped call, we can get NULL for operand 2. */ if (operands[2] == NULL_RTX) @@ -9097,18 +9097,13 @@ : !REG_P (callee)) XEXP (operands[0], 0) = force_reg (Pmode, callee); - pat = gen_call_internal (operands[0], operands[1], operands[2]); - arm_emit_call_insn (pat, XEXP (operands[0], 0)); - DONE; + }" + [] + "{ + arm_post_emit_call_insn (_val, XEXP (operands[0], 0)); }" ) -(define_expand "call_internal" - [(parallel [(call (match_operand 0 "memory_operand" "") - (match_operand 1 "general_operand" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))])]) - (define_insn "*call_reg_armv5" [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r")) (match_operand 1 "" "")) @@ -9191,7 +9186,7 @@ "TARGET_EITHER" " { - rtx pat, callee; + rtx callee; /* In an untyped call, we can get NULL for operand 2. */ if (operands[3] == 0) @@ -9205,21 +9200,13 @@ ? arm_is_long_call_p (SYMBOL_REF_DECL (callee)) : !REG_P (callee)) XEXP (operands[1], 0) = force_reg (Pmode, callee); - - pat = gen_call_value_internal (operands[0], operands[1], - operands[2], operands[3]); - arm_emit_call_insn (pat, XEXP (operands[1], 0)); - DONE; + }" + [] + "{ + arm_post_emit_call_insn (_val, XEXP (operands[1], 0)); }" ) -(define_expand "call_value_internal" - [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "memory_operand" "") - (match_operand 2 "general_operand" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))])]) - (define_insn "*call_value_reg_armv5" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:SI 1 "s_register_operand" "r")) diff --git a/gcc/genemit.c b/gcc/genemit.c index faaa610..aff27f6 100644 --- a/gcc/genemit.c +++ b/gcc/genemit.c @@ -422,7 +422,8 @@ gen_expand (rtx expand) /* If we don't have any C code to write, only one insn is being written, and no MATCH_DUPs are present, we can just return the desired insn like we do for a DEFINE_INSN. This saves memory. */ - if ((XSTR (expand, 3) == 0 || *XSTR (expand, 3) == '\0') + if (((XSTR (expand, 3) == 0 || *XSTR (expand, 3) == '\0')) + && (XSTR (expand, 5) == 0 || *XSTR (expand, 5) == '\0') && stats.max_opno >= stats.max_dup_opno && XVECLEN (expand, 1) == 1) { @@ -525,6 +526,23 @@ gen_expand (rtx expand) printf (" _val = get_insns ();\n"); printf (" end_sequence ();\n"); + + if (XSTR (expand, 5) && *XSTR (expand, 5)) + { + printf (" {\n"); + if (stats.num_operand_vars > 0) + printf (" rtx operands[%d];\n", stats.num_operand_vars); + + /* Output code to copy the arguments into `operands'. */ + for (i = 0; i < stats.num_generator_args; i++) + printf (" operands[%d] = operand%d;\n", i, i); + + print_md_ptr_loc (XSTR (expand, 5)); + printf ("%s\n", XSTR (expand, 5)); + + printf (" }\n"); + } + printf (" return _val;\n}\n\n"); } diff --git a/gcc/rtl.def b/gcc/rtl.def index 56418c7..655f752 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -933,8 +933,10 @@ DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) elements of `recog_data.operand' for use by the vector of insn-patterns. (`operands' is an alias here for `recog_data.operand'). - 5th: optionally, a vector of attributes for this expand. */ -DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA) + 5th: optionally, a vector of attributes for this expand. + 6th operand: Extra C code to execute after generating the insns. This code + is not executed if DONE (or FAIL) is used in the 4th operand. */ +DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssVs", RTX_EXTRA) /* Define a requirement for delay slots. 1st operand: Condition involving insn attributes that, if true, -- 1.8.3.2