From patchwork Mon Apr 28 10:46:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 343328 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5801E14009F for ; Mon, 28 Apr 2014 20:46:18 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=jMkCN81aeT0eiUQsn G1QOmBfkO/TlRMsmAZ8BuQgdWkYtcaYGMRV/J5OgqYoUQjebGCpQuVNxSiN9JFWi N8RwXm250VC9VCDvRcAO8Dh4bI4IWBRAFGgZmlWByPdBH1Dn2F4I7Nq0r6ZILJS4 eTUK0n1bmTcEP0d7ch3PsHtxtA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=0saq/YnoggaAwhbEdpwf0w/ J6uU=; b=iXDv34Dalxe6rYf9l+qdl/jm/YA/GdQHNGtda131TaeaaqhYqQ7q5X0 NnEJlSEoT3P1mypgxRe6UkwgsUVKi7a2ixd855MDJs2o9WRpQBWYdimIB2R3x1H2 QHcKAuzyQO0sbb7f6rW9uCZ1ppNFof5uPMyYH3ZqJ6nQeyaG6LOM= Received: (qmail 25722 invoked by alias); 28 Apr 2014 10:46:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25711 invoked by uid 89); 28 Apr 2014 10:46:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 28 Apr 2014 10:46:08 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 28 Apr 2014 11:46:06 +0100 Received: from [10.1.209.147] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 28 Apr 2014 11:46:18 +0100 Message-ID: <535E316B.7000603@arm.com> Date: Mon, 28 Apr 2014 11:46:03 +0100 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org, gcc-patches@gcc.gnu.org CC: Christophe Lyon Subject: [Patch ARM 2/3] Remove dead code from backend. References: <535E304D.7000800@arm.com> In-Reply-To: <535E304D.7000800@arm.com> X-MC-Unique: 114042811460604001 X-IsSubscribed: yes This then left us in the happy position of being able to delete code but I was worried about LTO streaming as these "builtins" are essentially streamed out in LTO object code format. However since we make no promises about LTO compatibility across releases, that's safe but I structured the dead code elimination as Patch 2/3. This will be committed separately in case folks want to backport Patch 1/3 separately and want to assure their users of LTO compatibility within a release branch (if that even works) . Ramana Radhakrishnan * config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf and v4sf versions. (vand, vorr, veor, vorn, vbic): Remove. * config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec, neon_vsub_unspec): Adjust iterator. (neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove. diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index a00951a..85215b5 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -18,8 +18,7 @@ along with GCC; see the file COPYING3. If not see . */ -VAR10 (BINOP, vadd, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +VAR2 (BINOP, vadd, v2sf, v4sf), VAR3 (BINOP, vaddl, v8qi, v4hi, v2si), VAR3 (BINOP, vaddw, v8qi, v4hi, v2si), VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si), @@ -54,7 +53,7 @@ VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si), VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -VAR10 (BINOP, vsub, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +VAR2 (BINOP, vsub, v2sf, v4sf), VAR3 (BINOP, vsubl, v8qi, v4hi, v2si), VAR3 (BINOP, vsubw, v8qi, v4hi, v2si), VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), @@ -199,14 +198,4 @@ VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di), VAR9 (STORESTRUCT, vst4, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), VAR7 (STORESTRUCTLANE, vst4_lane, - v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -VAR10 (LOGICBINOP, vand, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -VAR10 (LOGICBINOP, vorr, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -VAR10 (BINOP, veor, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -VAR10 (LOGICBINOP, vbic, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -VAR10 (LOGICBINOP, vorn, - v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) + v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index aad420c..9ac393b 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1842,9 +1842,9 @@ ; good for plain vadd, vaddq. (define_expand "neon_vadd" - [(match_operand:VDQX 0 "s_register_operand" "=w") - (match_operand:VDQX 1 "s_register_operand" "w") - (match_operand:VDQX 2 "s_register_operand" "w") + [(match_operand:VCVTF 0 "s_register_operand" "=w") + (match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i")] "TARGET_NEON" { @@ -1869,9 +1869,9 @@ ; Used for intrinsics when flag_unsafe_math_optimizations is false. (define_insn "neon_vadd_unspec" - [(set (match_operand:VDQX 0 "s_register_operand" "=w") - (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") - (match_operand:VDQX 2 "s_register_operand" "w")] + [(set (match_operand:VCVTF 0 "s_register_operand" "=w") + (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w")] UNSPEC_VADD))] "TARGET_NEON" "vadd.\t%0, %1, %2" @@ -2132,9 +2132,9 @@ ) (define_expand "neon_vsub" - [(match_operand:VDQX 0 "s_register_operand" "=w") - (match_operand:VDQX 1 "s_register_operand" "w") - (match_operand:VDQX 2 "s_register_operand" "w") + [(match_operand:VCVTF 0 "s_register_operand" "=w") + (match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i")] "TARGET_NEON" { @@ -2149,9 +2149,9 @@ ; Used for intrinsics when flag_unsafe_math_optimizations is false. (define_insn "neon_vsub_unspec" - [(set (match_operand:VDQX 0 "s_register_operand" "=w") - (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") - (match_operand:VDQX 2 "s_register_operand" "w")] + [(set (match_operand:VCVTF 0 "s_register_operand" "=w") + (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w")] UNSPEC_VSUB))] "TARGET_NEON" "vsub.\t%0, %1, %2" @@ -5357,61 +5357,6 @@ [(set_attr "type" "neon_store4_4reg")] ) -(define_expand "neon_vand" - [(match_operand:VDQX 0 "s_register_operand" "") - (match_operand:VDQX 1 "s_register_operand" "") - (match_operand:VDQX 2 "neon_inv_logic_op2" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_NEON" -{ - emit_insn (gen_and3 (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "neon_vorr" - [(match_operand:VDQX 0 "s_register_operand" "") - (match_operand:VDQX 1 "s_register_operand" "") - (match_operand:VDQX 2 "neon_logic_op2" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_NEON" -{ - emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "neon_veor" - [(match_operand:VDQX 0 "s_register_operand" "") - (match_operand:VDQX 1 "s_register_operand" "") - (match_operand:VDQX 2 "s_register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_NEON" -{ - emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "neon_vbic" - [(match_operand:VDQX 0 "s_register_operand" "") - (match_operand:VDQX 1 "s_register_operand" "") - (match_operand:VDQX 2 "neon_logic_op2" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_NEON" -{ - emit_insn (gen_bic3_neon (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "neon_vorn" - [(match_operand:VDQX 0 "s_register_operand" "") - (match_operand:VDQX 1 "s_register_operand" "") - (match_operand:VDQX 2 "neon_inv_logic_op2" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_NEON" -{ - emit_insn (gen_orn3_neon (operands[0], operands[1], operands[2])); - DONE; -}) - (define_insn "neon_vec_unpack_lo_" [(set (match_operand: 0 "register_operand" "=w") (SE: (vec_select: